Architectural design of an RISC processor for programmable logic controllers

作     者：Kyeonghoon, K Rho, GS Kwon, WH Park, J Chang, N 

作者机构：Seoul Natl Univ Sch Elect Engn Seoul 151742 South Korea Inha Univ Dept Ind Automat Inchon 402751 South Korea Seoul Natl Univ Dept Comp Engn Seoul South Korea 

出 版 物：《JOURNAL OF SYSTEMS ARCHITECTURE》 (系统结构杂志)

年 卷 期：1998年第44卷第5期

页      面：311-325页

核心收录：

学科分类：08[工学] 0835[工学-软件工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：reduced instruction set computer programmable logic controller relay ladder logic architecture 

摘      要：In this paper, an architecture of the RISC processor for programmable logic controllers is proposed. Execution characteristics of relay ladder logic (RLL) are analyzed with various application programs in order to determine an optimal architecture for programmable logic controllers (PLCs). A conditional execution mechanism is developed to prevent pipeline hazards caused by the inherent execution behavior of RLL. Instruction sets of three different architectural models are defined. Translators, assemblers, and simulators are developed for three models to evaluate performance and to choose an optimal architecture for PLCs. The proposed processor, which has an accumulator architecture with a four-stage pipeline, exhibits desirable performance much higher than that of recent commercial PLCs.