Reconfigurable pipelined 2-D convolvers for fast digital signal processing

作     者：Bosi, B Bois, G Savaria, Y 

作者机构：Nortel Nepean ON K2H 8V4 Canada Ecole Polytech Dept Elect & Comp Engn Montreal PQ H3C 3A7 Canada 

出 版 物：《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 (IEEE Trans Very Large Scale Integr VLSI Syst)

年 卷 期：1999年第7卷第3期

页      面：299-308页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Natural Sciences and Engineering Research Council of Canada  NSERC  (OGP0006574) 

主　　题：architectural tradeoffs custom computing machine design methodology design reuse DSP function library hardware/software co-design reconfigurable hardware accelerator 

摘      要：In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer s toolset. In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work. Complex signal transformations then become function calls, e.g., C-callable functions. Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP s, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming. Therefore, the exploration of the 2-D convolver s design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors. Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed, In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated, Dallas, TX, However, the proposed concept is not limited to a particular processor.