On-line fault detection for bus-based field programmable gate arrays

作     者：Shnidman, NR Mangione-Smith, WH Potkonjak, M 

作者机构：MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA MIT Dept Comp Sci Cambridge MA 02139 USA 

出 版 物：《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 (IEEE Trans Very Large Scale Integr VLSI Syst)

年 卷 期：1998年第6卷第4期

页      面：656-666页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：National Science Foundation  NSF 

主　　题：digital system fault tolerance field programmable gate arrays self-testing 

摘      要：We introduce a technique for on-line built-in self-testing (BIST) of bus-based held programmable gate arrays (FPGA s), This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device s internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system.