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作者机构:Cornell Univ Sch Elect Engn Ithaca NY 14853 USA Stanford Univ Comp Syst Lab Stanford CA 94305 USA Microsoft Corp Res Redmond WA 98052 USA
出 版 物:《IEEE TRANSACTIONS ON COMPUTERS》 (IEEE Trans Comput)
年 卷 期:1999年第48卷第2期
页 面:205-217页
核心收录:
学科分类:0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术(可授工学、理学学位)]
基 金:National Science Foundation, NSF Defense Advanced Research Projects Agency, DARPA, (DABT63-94-C-0054) Defense Advanced Research Projects Agency, DARPA
主 题:cache coherence protocols distributed shared memory FLASH MAGIC performance comparison scalable multiprocessors flexible node controller bitvector SCI COMA dynamic pointer allocation controller occupancy
摘 要:Scalable cache coherence protocols have become the key technology for creating moderate to large-scale shared-memory multiprocessors. Although the performance of such multiprocessors depends critically on the performance of the cache coherence protocol, little comparative performance data is available. Existing commercial implementations use a variety of different protocols, including bit-vector/coarse-vector protocols, SCI-based protocols, and COMA protocols. Using the programmable protocol processor of the Stanford FLASH multiprocessor, we provide a detailed, implementation-oriented evaluation of four popular cache coherence protocols. In addition to measurements of the characteristics of protocol execution (e.g., memory overhead, protocol execution time, and message count) and of overall performance, we examine the effects of scaling the processor count from 1 to 128 processors. Surprisingly, the optimal protocol changes for different applications and can change with processor count even within the same application. These results help identify the strengths of specific protocols and illustrate the benefits of providing flexibility in the choice of cache coherence protocol.