PLD code reveals pc-board revisions

作     者：Bolton, C 

作者机构：Bolton Engn Inc Melrose MA 02176 USA 

出 版 物：《EDN》 (EDN)

年 卷 期：2002年第47卷第23期

页      面：102-+页

核心收录：

主　　题：Programmable logic controllers 

摘      要：The programmable-logic-device (PLD) code implements a pc-board-level revision-detection system that detects whether PLD pins are shorted together on a pc board. In PLD families that have no integral pin-pullup or pulldown resistors, redefining previously unused pins as inputs means that these pins float, either causing erratic operation or indicating an improper pc-board-revision level. The software module generates a short, simple pattern, such as a square wave, onto a driver pin, REVO_OUT. An implementation of the design with the parameters set to the default values takes 16 logic cells in an Altera EP1K50BC256-3-less than 1% of the device and runs at rates as high as 185 MHz.