Routability improvement using dynamic interconnect architecture

作     者：Li, JM Cheng, CK 

作者机构：Synopsys Inc Mt View CA 94043 USA Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA 

出 版 物：《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 (IEEE Trans Very Large Scale Integr VLSI Syst)

年 卷 期：1998年第6卷第3期

页      面：498-501页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：National Science Foundation  NSF  (MIP-9529077) 

主　　题：computer-aided design (CAD) channel routing computing architecture field programmable gate array (FPGA) interconnection 

摘      要：We present a dynamic architecture for field programmable gate array (FPGA)-based computing systems with the introduction of dynamic field-programmable interconnection devices. The central principle of this new architecture is based on the concept of time-sharing, which we use to efficiently exploit the potential communication bandwidth of interconnection resources. This new architecture not only releases FPGA pin limitation to some degree, but also greatly increases the routability of interconnection networks, resulting in higher overall performance of FPGA-based systems.