Design for testability techniques at the behavioral and register-transfer levels

作     者：Dey, S Raghunathan, A Wagner, KD 

作者机构：Univ Calif San Diego Dept ECE La Jolla CA 92093 USA NEC USA C&C Res Labs Princeton NJ 08540 USA Siemens Microelect Inc San Jose CA USA 

出 版 物：《JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS》 (电子测试杂志；理论与应用)

年 卷 期：1998年第13卷第2期

页      面：79-91页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：behavioral synthesis for testability behavioral synthesis for BIST design for testability high-level test generation RTL synthesis for testability 

摘      要：Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.