High Bandwidth Efficiency and Low Power Consumption Walsh Code Implementation Methods for Body Channel Communication

作     者：Ho, Chee Keong Cheong, Jia Hao Lee, Junghyup Kulkarni, Vishal Li, Peng Liu, Xin Je, Minkyu 

作者机构：ASTAR Inst Microelect Singapore 117685 Singapore Daegu Gyeongbuk Inst Sci & Technol Dept Informat & Commun Engn Taegu 711873 South Korea 

出 版 物：《IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES》 (IEEE Trans. Microwave Theory Tech.)

年 卷 期：2014年第62卷第9期

页      面：1867-1878页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

基　　金：Agency for Science  Technology and Research (A*STAR) Science and Engineering Research Council (SERC) Singapore  under NeuroDevices Program [102 171 0161/0162/0163] 

主　　题：Frequency-selective digital transmission (FSDT) harmonic frequency human body communication synchronization Walsh code wireless 

摘      要：With the growing number of wearable devices and applications, there is an increasing need for a flexible body channel communication (BCC) system that supports both scalable data rate and low power operation. In this paper, a highly flexible frequency-selective digital transmission (FSDT) transmitter that supports both data scalability and low power operation with the aid of two novel implementation methods is presented. In an FSDT system, data rate is limited by the number of Walsh spreading codes available for use in the optimal body channel band of 40-80 MHz. The first method overcomes this limitation by applying multi-level baseband coding scheme to a carrierless FSDT system to enhance the bandwidth efficiency and to support a data rate of 60 Mb/s within a 40-MHz bandwidth. The proposed multi-level coded FSDT system achieves six times higher data rate as compared to other BCC systems. The second novel implementation method lies in the use of harmonic frequencies of a Walsh encoded FSDT system that allows the BCC system to operate in the optimal channel bandwidth between 40-80 MHz with half the clock frequency. Halving the clock frequency results in a power consumption reduction of 32%. The transmitter was fabricated in a 65-nm CMOS process. It occupies a core area of 0.24 x 0.3 mm(2). When operating under a 60-Mb/s data-rate mode, the transmitter consumes 1.85mW and it consumes only 1.26 mW when operating under a 5-Mb/s data-rate mode.