Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression

作     者：Masoudnia, A Sarbazi-Azad, H Boussakta, S 

作者机构：IPM Inst Studies Theoret Phys & Math Sch Comp Sci Tehran Iran Sharif Univ Technol Dept Comp Engn Tehran Iran Univ Leeds Sch Elect & Elect Engn Leeds LS2 9JT W Yorkshire England 

出 版 物：《COMPUTERS & ELECTRICAL ENGINEERING》 (计算机与电工)

年 卷 期：2005年第31卷第8期

页      面：572-588页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：image processing compression decompression wavelet transform serial-parallel architecture pipelining FPGA implementation performance 

摘      要：Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 x 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time. (c) 2005 Elsevier Ltd. All rights reserved.