Area and speed oriented synthesis of FSMs for PAL-based CPLDs

作     者：Czerwinski, R. Kania, D. 

作者机构：Silesian Tech Univ Inst Elect PL-44100 Gliwice Poland 

出 版 物：《MICROPROCESSORS AND MICROSYSTEMS》 (微处理机与微型系统)

年 卷 期：2012年第36卷第1期

页      面：45-61页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Logic synthesis FSM State assignment Logic optimization CPLD 

摘      要：New two-step methods of FSMs synthesis for PAL-based CPLDs are presented in the paper. The methods strive to find the optimum fit for a FSM to the structure of CPLD and aim at area and speed optimization. The first step for both methods is original state assignment that includes: techniques of two-level minimization, the limited number of terms contained in the cell and elements of adjusting to the logic optimization. The second step in the method oriented toward area minimization is PAL-oriented multi-level optimization, which is a search for implicants that can be shared by several functions. The second step in the method oriented toward speed maximization is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block. (C) 2011 Elsevier B.V. All rights reserved.