High-performance Syndrome-based SD-BCH Decoder Architecture using Hard-decision Kernel

作     者：Kim, Taesung Lee, Hanho 

作者机构：Inha Univ Dept Informat & Commun Engn Incheon 22212 South Korea 

出 版 物：《JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE》 (J. Semicond. Technol. Sci.)

年 卷 期：2018年第18卷第6期

页      面：694-703页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0702[理学-物理学] 

基　　金：Basic Science Research Program through the NRF - MSIT(Ministry of Science, ICT) [2016R1A2B4015421] MSIT, Korea under the ITRC support program [IITP-2018-2014-1-00729] 

主　　题：BCH codes soft-decision decoding decoder modified step-by-step algorithm 

摘      要：This paper proposes a high-performance, low-complexity, soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and its efficient design techniques. The proposed SD-BCH decoder not only uses the test syndrome computation, but also non-iteration processes. The proposed (1020, 990) SD-BCH decoder achieves a 0.75 dB higher coding gain compared to the (1020, 990) hard-decision BCH (HD-BCH) decoder. The proposed SD-BCH decoder was designed and implemented using the 65-nm CMOS technology. The synthesis results show that the proposed SD-BCH decoder architecture with serial structure (P = 1) has 24.7K gate count, which leads to a 69% reduction in hardware complexity compared to the previous SD-BCH decoder architecture.