TERAFLUX: Harnessing dataflow in next generation teradevices

作     者：Giorgi, Roberto Badia, Rosa M. Bodin, Francois Cohen, Albert Evripidou, Paraskevas Faraboschi, Paolo Fechner, Bernhard Gao, Guang R. Garbade, Arne Gayatri, Rahul Girbal, Sylvain Goodman, Daniel Khan, Behran Koliai, Souad Landwehr, Joshua Nhat Minh Le Li, Feng Lujan, Mikel Mendelson, Avi Morin, Laurent Navarro, Nacho Patejko, Tomasz Pop, Antoniu Trancoso, Pedro Ungerer, Theo Watson, Ian Weis, Sebastian Zuckerman, Stephane Valero, Mateo 

作者机构：Univ Siena Dip Ingn Informaz & Sci Matemat I-53100 Siena Italy Barcelona Supercomp Ctr Barcelona Spain CAPS Enterprise Paris France INRIA Paris France Univ Cyprus Dept Comp Sci Nicosia Cyprus Hewlett Packard Corp Intelligent Infrastruct Lab Barcelona Spain Univ Augsburg Augsburg Germany Univ Delaware Newark DE 19716 USA THALES Paris France Univ Manchester Manchester M13 9PL Lancs England Technion Israel Inst Technol IL-32000 Haifa Israel 

出 版 物：《MICROPROCESSORS AND MICROSYSTEMS》 (微处理机与微型系统)

年 卷 期：2014年第38卷第8期

页      面：976-990页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：European FP7 Project TERAFLUX Spanish Ministry of Science and Innovation [TIN2012-34557] Generalitat de Catalunya [2009-SGR-980] 

主　　题：Dataflow Programming model Compilation Reliability Architecture Simulation Many-cores Exascale computing Multi-cores 

摘      要：The improvements in semiconductor technologies are gradually enabling extreme-scale systems such as teradevices (i.e., chips composed by 1000 billion of transistors), most likely by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper presents an overview of the research carried out by the TERAFLUX partners and some preliminary results. Our platform comprises 1000+ general purpose cores per chip in order to properly explore the above challenges. An architectural template has been proposed and applications have been ported to the platform. Programming models, compilation tools, and reliability techniques have been developed. The evaluation is carried out by leveraging on modifications of the HP-Labs COTSon simulator. (C) 2014 Elsevier B.V. All rights reserved.