Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor

作     者：范宝峡 杨梁 王江嵋 王茹 肖斌 徐英 刘动 赵继业 

作者机构：Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences Loongson TechnologyCorporation Limited 

出 版 物：《Journal of Computer Science & Technology》 (计算机科学技术学报（英文版）)

年 卷 期：2010年第25卷第2期

页      面：192-199页

核心收录：

学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by the National Basic Research 973 Program of China under Grant No.2005CB321600 the National High Technology Research & Development 863 Program of China under Grant Nos.2008AA110901,2009AA01Z125 and 2007AA01Z114 the National Natural Science Foundation of China under Grant Nos.60803029,60673146,60736012 

主　　题：physical implementation design methodology on-chip variation （OCV） low power clock tree 

摘      要：The Godson-3A microprocessor is a quad-core version of the scalable Godson-3 multi-core series. It is physically implemented based on the 65 nm CMOS process. This 174 mm2 chip consists of 425 million transistors. The maximum frequency is 1GHz with a maximum power consumption of 15 W. The main challenges of Godson-3A physical implementation include very large scale, high frequency requirement, sub-micron technology effects and aggressive time schedule. This paper describes the design methodology of the physical implementation of Godson-3A, with particular emphasis on design methods for high frequency, clock tree design, power management, and on-chip variation （OCV） issue.