Analysis and Design of a ΔΣ Modulator for Fractional-N Frequency Synthesis

作     者：张伟超 许俊 郑增钰 任俊彦 Zhang Weichao;Xu Jun;Zheng Zengyu;Ren Junyan

作者机构：复旦大学微电子学系专用集成电路与系统国家重点实验室上海200433 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2006年第27卷第1期

页      面：41-46页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：上海应用材料研究与发展基金资助项目(批准号:0302) 

主　　题：△∑ modulator fractional-N frequency synthesis MASH architecture 

摘      要：This paper presents the design considerations and implementation of a novel topology digital multistage-noise-shaping （MASH） delta-sigma modulator suitable for fractional-N phase-locked-loop （PLL） frequency synthesis. In an effort to reduce the complexity and dissipation,a pipeline technique has been used, and the proposed carry save tree （CST） algorithm optimizes the multi-input adder structure. The circuit has been verified through Matlab simulation, ASIC implementation, and FPGA experiment, which exhibits high performance and potential for a gigahertz range,low-power monolithic CMOS frequency synthesizer.