Image compression sensor based on column parallel architecture

作     者：Hamamoto, T Aizawa, K Hatori, M 

作者机构：Univ Tokyo Dept Elect Engn Hatori Aizawa Lab Bunkyo Ku Tokyo 113 Japan 

出 版 物：《COMPUTERS & ELECTRICAL ENGINEERING》 (Comput Electr Eng)

年 卷 期：1997年第23卷第6期

页      面：463-473页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：compression smart sensor computational sensor intelligent sensor CMOS sensor conditional replenishment column parallel architecture 

摘      要：We propose a novel image sensor which has compression function on its sensor plane. The image compression sensor can significantly reduce the amount of pixel data output from the sensor. The proposed sensor is intended to overcome the communication bottle neck for high pixel rate imaging such as high frame rate imaging and high resolution imaging. The compression algorithm is based on conditional replenishment. It detects motion and encodes only the pixels in moving areas. We have been investigating pixel parallel and column parallel architectures of the image compression sensor. In this paper, we present the column parallel architecture of the proposed sensor. In this architecture, fill factor and power dissipation are comparable to conventional MOS sensors in spite of integration of the processing circuits. We have fabricated a prototype chip based on the column parallel architecture. We describe the circuit and layout design and the results of some experiments using the prototype. (C) 1998 Elsevier Science Ltd. All rights reserved.