CAA decoder for Cellular Automata based byte error correcting code

作     者：Sasidhar, K Chattopadhyay, S Chaudhuri, PP 

作者机构：DEEMED UNIVBENGAL ENGN COLLDEPT COMP SCI & TECHNOLHOWRAH 711103INDIA INDIAN INST TECHNOLDEPT COMP SCI & ENGNKHARAGPUR 721302W BENGALINDIA 

出 版 物：《IEEE TRANSACTIONS ON COMPUTERS》 (IEEE Trans Comput)

年 卷 期：1996年第45卷第9期

页      面：1003-1016页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：cellular automata error correcting code cellular automata array (CAA) error vector error space 

摘      要：Design of Cellular Automata (CA) based byte error correcting code analogous to extended Reed-Solomon code has been proposed in [1], [2]. This code has same restrictions on error correction as that of extended R-S code. In this paper a new design scheme has been reported for parallel implementation of CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) with high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme to detect/correct larger number of byte errors has also been reported. Throughput of the decoder to handle t byte errors (t less than or equal to 4) can be found to be substantially better than that of conventional R-S decoder. The proposed decoder provides a simple, modular and cost effective design that ideally suits for VLSI implementation.