Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

作     者：DeHon, Andre 

作者机构：Univ of California at Berkeley Berkeley CA United States 

出 版 物：《ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA》 (ACM SIGDA Int Symp Field Program Gate Arrays)

年 卷 期：1999年

页      面：69-78页

核心收录：

主　　题：Field programmable gate arrays 

摘      要：FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficient silicon usage. Rather, since interconnect resources consume most of the area on these devices (often 80-90%), we can achieve more area efficient designs by allowing some LUTs to go unused - allowing us to use the dominant resource, interconnect, more efficiently. This extends the `Sea-of-gates philosophy, familiar to mask programmable gate arrays, to FPGAs. Also introduced in this work is an algorithm for `depopulating the gates in a hierarchical network to match the limited wiring resources.