Loop regularization for image and video processing on instruction level parallel architectures

作     者：Zingirian, N. Maresca, M. 

作者机构：Univ of Padova Padova Italy 

出 版 物：《Computer Architectures for Machine Perception, Proceedings (CAMP)》 (Comput Archit Mach Percept CAMP Proc)

年 卷 期：2000年

页      面：261-269页

核心收录：

主　　题：Parallel processing systems 

摘      要：This paper presents a novel loop transformation (Loop Regularization, LR) that increases the execution efficiency of Image and Video Processing programs running on instruction level parallel (ILP) processors. LR is specifically devised for those ILP processors that do not include hardware mechanisms for instruction reordering and register renaming such as today s low cost processors for embedded systems and digital signal processors. This paper shows the effects of LR and reports on a set of system-level experiments that validate the technique.