Improved Decimal Floating-Point Logarithmic Converter Based on Selection by Rounding

作     者：Chen, Dongdong Han, Liu Choi, Younhee Ko, Seok-Bum 

作者机构：Univ Saskatchewan Dept Elect & Comp Engn Sasaktoon SK S7N 5A9 Canada 

出 版 物：《IEEE TRANSACTIONS ON COMPUTERS》 (IEEE Trans Comput)

年 卷 期：2012年第61卷第5期

页      面：607-621页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Natural Sciences and Engineering Research Council of Canada (NSERC) 

主　　题：Decimal floating-point decimal logarithmic converter digit-recurrence algorithm selection by rounding 

摘      要：This paper presents the algorithm and architecture of the decimal floating-point (DFP) logarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP logarithm results for any one of the three DFP formats specified in the IEEE 754-2008 standard. In order to optimize the latency for the proposed design, we mainly integrate the following novel features: 1) using the redundant carry-save representation of the data path;2) reducing the number of iterations by determining the number of initial iteration;and 3) retiming and balancing the delay of the proposed architecture. The proposed architecture is synthesized with STM 90-nm standard cell library and the results show that the critical path delay and the number of clock cycles of the proposed Decimal64 logarithmic converter are 1.55 ns (34.4 FO4) and 19, respectively, and the total hardware complexity is 43,572 NAND2 gates. The delay estimation results of the proposed architecture show that its latency is close to that of the binary radix-16 logarithmic converter, and that it has a significant decrease on latency compared with a recently published high performance CORDIC implementation.