Impact of Supply Voltage and Frequency on the Soft Error Rate of Logic Circuits

作     者：Mahatme, N. N. Gaspard, N. J. Jagannathan, S. Loveless, T. D. Bhuva, B. L. Robinson, W. H. Massengill, L. W. Wen, S-J Wong, R. 

作者机构：Vanderbilt Univ Dept Elect Engn & Comp Sci Nashville TN 37212 USA 

出 版 物：《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》 (IEEE Trans Nucl Sci)

年 卷 期：2013年第60卷第6期

页      面：4200-4206页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0827[工学-核科学与技术] 

基　　金：CISCO Systems Inc U. S. Defense Threat Reduction Agency 

主　　题：Combinational logic high frequency circuits soft error rate supply voltage variation 

摘      要：Alpha particle irradiations of 28-nm combinational logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the combinational logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from combinational logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.