An efficient technique to select logic nodes for single event transient pulse-width reduction

作     者：Mahatme, Nihaar N. Chatterjee, Indranil Patki, Akash Limbrick, Daniel B. Bhuva, Bharat L. Schrimpf, Ronald D. Robinson, William 

作者机构：Vanderbilt Univ Dept Elect Engn & Comp Sci Nashville TN 37212 USA 

出 版 物：《MICROELECTRONICS RELIABILITY》 (微电子学可靠性)

年 卷 期：2013年第53卷第1期

页      面：114-117页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0702[理学-物理学] 

基　　金：Division of Computing and Communication Foundations Direct For Computer & Info Scie & Enginr Funding Source: National Science Foundation 

主　　题：SINGLE event effects (Electronics) ERROR rates TRANSIENTS (Electricity) LOGIC circuits PULSE modulation (Electronics) PULSE-width modulation 

摘      要：An efficient method has been developed to identify logic nodes most likely to generate single-event transients due to p-hits or n-hits. This is weighed against the logical masking effect of gates. Selected gates are hardened by increasing widths of only the restoring devices to reduce single-event error rate. (C) 2012 Elsevier Ltd. All rights reserved.