An area-efficient bit-serial sequential polynomial basis finite field GF (2<SUP>m</SUP>) multiplier

作     者：Pillutla, Siva Ramakrishna Boppana, Lakshmi 

作者机构：Natl Inst Technol Warangal Dept Elect & Commun Engn Fathimanagar Telangana India 

出 版 物：《AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS》 (AEU Int. J. Electron. Commun.)

年 卷 期：2020年第114卷

核心收录：

学科分类：0810[工学-信息与通信工程] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：Finite field arithmetic Polynomial basis Bit-serial multiplier Elliptic curve cryptography Internet of Things (IoT) 

摘      要：Many cryptographic and error control coding algorithms rely on finite field arithmetic. Hardware implementation of these algorithms requires an efficient realization of finite field GF(2(m)) arithmetic operations. Finite field multiplication is complex among the basic arithmetic operations, and it is employed in field exponentiation and inversion operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a modified interleaved modular reduction multiplication algorithm and its bit-serial sequential architecture are proposed. It is observed from the comparison of analytical results that the proposed architecture achieves the reduction in area and area-delay product compared to the existing multipliers. The proposed multiplier achieves an improvement of 39% in area and 17% in area-delay product estimations for field order of 409 when compared with the best sequential multiplier available in the literature. Application specific integrated circuit (ASIC) implementation of the proposed multiplier together with the two most comparable multipliers confirms that the proposed multiplier outperforms in terms of area and area-delay product. The proposed multiplier is suitable for implementation of security in Internet of Things (IoT) gateways and edge-devices. (C) 2019 Elsevier GmbH. All rights reserved.