CNNP-v2: A Memory-Centric Architecture for Low-Power CNN Processor on Domain-Specific Mobile Devices

作     者：Choi, Sungpill Bong, Kyeongryeol Han, Donghyeon You, Hoi-Jun 

作者机构：Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea 

出 版 物：《IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS》 

年 卷 期：2019年第9卷第4期

页      面：598-611页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

基　　金：Institute for Information & Communications Technology Promotion (IITP) - Korean Government [2017-0-01803] 

主　　题：Memory architecture Digital circuits Energy efficiency Integrated circuit interconnections Convolutional neural networks Face recognition Convolutional neural network (CNN) memory-centric architecture low-power image processing energy-efficient digital circuit 

摘      要：An energy-efficient memory-centric convolutional neural network (CNN) processor architecture is proposed for smart devices such as wearable devices or the internet of things (IoT) devices. To achieve energy-efficient processing, it has two key features: First, 1-D shift convolution PEs with fully distributed memory architecture achieve 1.5TOPS/W energy efficiency, and it can be boosted up equivalent 3.1TOPS/W energy efficiency with separable filter approximation and transpose-read SRAM. Compared with conventional architecture, even though it has massively parallel 1024 MAC units, it achieves high energy efficiency by scaling down the voltage to 0.46V due to its fully local routed design. Second, fully configurable 2-D mesh core-to-core interconnection support the various size of input features to maximize utilization. The proposed architecture is evaluated 16mm(2) chip, which is fabricated with a 65nm CMOS process. As a result, it performs real-time face recognition with the only 68.9mW at 40MHz and 0.6V.