this book constitutes the refereed proceedings of the 10thasia-pacificcomputersystemsarchitectureconference, ACSAC 2005, held in Singapore in October *** 65 revised full papers presented were carefully reviewed a...
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ISBN:
(数字)9783540321088
ISBN:
(纸本)9783540296430
this book constitutes the refereed proceedings of the 10thasia-pacificcomputersystemsarchitectureconference, ACSAC 2005, held in Singapore in October *** 65 revised full papers presented were carefully reviewed and selected from 173 submissions. the papers are organized in topical sections on energy efficient and power aware techniques, methodologies and architectures for application-specific systems, processor architectures and microarchitectures, high-reliability and fault-tolerant architectures, compiler and OS for emerging architectures, data value predictions, reconfigurable computing systems and polymorphic architectures, interconnect networks and network interfaces, parallel architectures and computation models, hardware-software partitioning, verification, and testing of complex architectures, architectures for secured computing, simulation and performance evaluation, architectures for emerging technologies and applications, and memory systems hierarchy and management.
As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for c...
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ISBN:
(纸本)0780387368
As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraint-driven synthesis is not feasible anymore. In this paper we propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Our approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies the constraints in a design.
Architectural exploration is very important in embedded system design and SoC design. In this paper, a new heuristic algorithm using the allocation-on-demand technique is proposed to solve this problem. Unlike previou...
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ISBN:
(纸本)0780387368
Architectural exploration is very important in embedded system design and SoC design. In this paper, a new heuristic algorithm using the allocation-on-demand technique is proposed to solve this problem. Unlike previous research efforts, this algorithm allocates new resources only when it fails to schedule tasks under the performance constraints. So the resource costs of the system increase monotonously in running, which is apt to determine the feasibility of current solution earlier. Experimental results show that this approach is helpful for an efficient architectural exploration process.
Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code in the...
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ISBN:
(纸本)3540400567
Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of registers for inserting optimization code in the main program. It is difficult to achieve both correctness and transparency when software-only schemes for acquiring registers are used, as described in [1]. We propose an architecture feature that builds upon existing hardware for stacked register allocation on the Itanium processor. the hardware impact of this feature is minimal, while simultaneously allowing post-link and dynamic optimization systems to obtain registers for optimization in a "safe" manner, thus preserving the transparency and improving the performance of these systems.
computer graphics and high-resolution digital imagery are becoming increasingly pervasive in communities not traditionally associated with graphics. Commodity graphics cards and digital cameras, along with powerful mo...
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ISBN:
(纸本)0769517846;0769517854
computer graphics and high-resolution digital imagery are becoming increasingly pervasive in communities not traditionally associated with graphics. Commodity graphics cards and digital cameras, along with powerful modeling software, allow organizations such as libraries, museums, and small businesses to produce expressive and realistic computer generated imagery,, far surpassing the capabilities of current desktop monitors. What remains elusive to these groups is access to affordable and easy to use large format display technology. We present a practical system for deploying flexible projector-based tiled displays. Our framework integrates two key components: (1) self-calibrating display geometry with real-time geometric correction and (2) PC-based distributed rendering that supports an established graphics API. Our system's display geometry is easy to configure and reconfigure, accommodates casually tiled projectors and arbitrary display surfaces, and can be operational in a matter of minutes. In addition, the underlying distributed rendering architecture (WireGL) is transparent to existing OpenGL applications, requiring no custom APIs or re-compilation of existing OpenGL executables. In short, we present a practical and flexible low-cost tiled display system that is simple to deploy and easy to operate.
this paper proposes a simple message passing detector with QR-decomposition for multi-input multi-output ( MIMO) systems. Our message passing algorithm exploits the structure of QR-decomposed received signals and achi...
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ISBN:
(纸本)9789881476852
this paper proposes a simple message passing detector with QR-decomposition for multi-input multi-output ( MIMO) systems. Our message passing algorithm exploits the structure of QR-decomposed received signals and achieves optimum maximum likelihood ( ML) detection with less complexity. computer simulations confirm the superior performance of our proposed approach to conventional message passing techniques such as belief propagation ( BP).
New trends in the space industry, e.g. the development of wireless networked constellations using miniaturized satellites, have generated a pressing need for condition-based maintenance, self-repair and upgrade capabi...
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ISBN:
(纸本)3540400567
New trends in the space industry, e.g. the development of wireless networked constellations using miniaturized satellites, have generated a pressing need for condition-based maintenance, self-repair and upgrade capabilities on-board satellites. this can be achieved by using reconfigurable hardware technologies, such as high-density Field Programmable Gate Arrays, implementing an entire on-board computer on a single chip. In this paper we present a system-on-chip architecture for on-board partial run-time reconfiguration to enable system-level functional changes on-board satellites ensuring correct operation, longer life and higher quality of service.
this paper evaluates a novel media access control (MAC) method with multiple frame transmission that increases the throughput performance of high speed wireless local area network (LAN) systems. the current MAC protoc...
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ISBN:
(纸本)0780386019
this paper evaluates a novel media access control (MAC) method with multiple frame transmission that increases the throughput performance of high speed wireless local area network (LAN) systems. the current MAC protocol has two problems when used in high speed wireless LAN systems: poor efficiency and the failure to match for a multirate mechanism. the frame bursting method solves these problems by allowing multiple frames to be transmitted within one media access period. In this paper, the performance evaluations of the frame bursting method are performed by computer simulation. the results demonstrate that the frame bursting method can achieve higher system throughput, 10 Mbit/s, than the system throughput performance of conventional systems. Moreover, the results shows that the frame bursting method works well in the wireless LAN systemsthat employ the multirate mechanism and can achieve higher throughput performance.
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than one instruction per each cycle. the ...
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this paper introduces LEAP(Loop Engine on Array Processor), a novel coarse-grained reconfigurable architecture which accelerates applications through Loop Self-Pipelining (LSP) technique. the LSP can provide effective...
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ISBN:
(纸本)3540400567
this paper introduces LEAP(Loop Engine on Array Processor), a novel coarse-grained reconfigurable architecture which accelerates applications through Loop Self-Pipelining (LSP) technique. the LSP can provide effective execution mode for application pipelining. By mapping and distributing the expression statements of high level programming languages onto processing elements array, the LEAP can step the loop iteration automatically. the LEAP architecture has no centralized control, no centralized multi-port registers and no centralized data memory. the LEAP has the ability to exploit loop-level, instruction-level, and task-level parallelism, and it is suitable choice for stream-based application domains, such as multimedia, DSP and graphics application.
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