作者:
Van Der Werf, Steven M.Chung, Kah-Seng
Department of Electrical and Computer Engineering Curtin University of Technology GPO Box U1987 Perth WA 6845 Australia
this paper presents a new fully distributed Multi-hop Wireless Ad-hoc Routing Protocol (MultiWARP) that aims at minimizing the number of route request (RREQ) packets transmitted between nodes in a directed way, which ...
详细信息
this paper describes a method of human short hair modeling and real time animation. A method is proposed to model the short hair First, a hair style model is derived from a scalp model interactively. then, the hair mo...
详细信息
ISBN:
(纸本)0769517846;0769517854
this paper describes a method of human short hair modeling and real time animation. A method is proposed to model the short hair First, a hair style model is derived from a scalp model interactively. then, the hair model is derived automatically from the hair style and scalp models. Texture mapping is applied to hair model for a better visual effect. For animation, a method is proposed based on an approximation of the accurate physically-based hair model, from which the 3D morphing key shapes are derived. then, the intermediate shapes are computed by applying 3D morphing. We have implemented it and compared the results with real hair the visual quality and frame rate are satisfactory for real time applications.
Formulated the problem of the enormous difficulties faced by visually impaired people to access written information in visual means, the results of a preliminary software model for recognizing basic geometrical shapes...
详细信息
While lots of prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. this is unfortunate since in general the performance-oriented techniques in...
详细信息
ISBN:
(纸本)0780387368
While lots of prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. this is unfortunate since in general the performance-oriented techniques influence energy behavior of the cache, and the energy-oriented techniques usually increase program execution cycles. the overall energy and performance behavior of caches in embedded systems when multiple techniques co-exist remains an open research problem. this paper studies this interaction and illustrates how performance and energy optimizations affect each other. We also point out several potential optimizations that could be based on this study.
the article describes a solution for monitoring the presence and movement of workers between production halls in the factory. the physical structure of the monitoring system components based on RFID antennas and chips...
详细信息
ISBN:
(纸本)9783030201456;9783030201449
the article describes a solution for monitoring the presence and movement of workers between production halls in the factory. the physical structure of the monitoring system components based on RFID antennas and chips embedded in every clothing element of an employee is presented. the hardware and software architecture of the solution is also presented and described in the article. Particular attention was paid to the algorithmic issues related to the detection of ambiguities resulting from human-machine cooperation. A number of problems resulting from different behavior of employees and their interpretation on the basis of readings for individual elements of their work attire have been solved.
We introduce a novel architecture template modeling for mapping applications on coarse-grained reconfigurable SoC. System level design issues become critical with increasingly complex integrated circuits and time-to-m...
详细信息
ISBN:
(纸本)9781424415786
We introduce a novel architecture template modeling for mapping applications on coarse-grained reconfigurable SoC. System level design issues become critical with increasingly complex integrated circuits and time-to-market pressure continues relentlessly. Design reuse and early design decision for computation and communication are a "must". Our technique is based on a transaction level architecture template modeling methodology in which computation/communication co-design is performed withthe architecture described in an abstract manner. Besides, we use eACOGA algorithm for hw/sw partition. eACOGA uses genetic algorithm to evolve the parameters of ant colony optimization, and makes use of such advantages as positive feedback and efficient convergence to search for optimal partition solutions. Experiments show our approach improves the quality and efficiency of hw/sw partition for. reconfigurable SoC, and architecture template enhances system reuse of existing SoC design and achieves exploration speedup well.
Dynamic data redistribution enhances data locality and improves algorithm performance for numerous scientific problems on distributed memory multi-computers systems. Previous results focus on reducing index computatio...
详细信息
Intelligent city traffic for travelling navigation, traffic prediction and decision support needs to collect large-scale real-time data from numerous vehicles. As a small, economical yet reasonably efficient device, w...
详细信息
ISBN:
(纸本)3540400567
Intelligent city traffic for travelling navigation, traffic prediction and decision support needs to collect large-scale real-time data from numerous vehicles. As a small, economical yet reasonably efficient device, wireless sensors can conveniently serve for this purpose. In this paper(1), we investigate how to deploy wireless sensor networks in buses to gather traffic data for intelligent city traffic. the paper presents a selforganization mechanism and a routing protocol for the proposed sensor networks. Our work has three advantages: (1)adaptive network topology, which satisfies highly mobile city traffic environment, (2)directed data transmission, saving energy consumption of sensor nodes with limited power resource, and (3)longer lifetime because of fewer redundant network communication and balanced power usage of sensor nodes in a network.
Most approaches to interface synthesis take two interface FSMs including transactions or burst, derive a product FSM and generate an interface circuit from the product FSM. Withthese methods, it could be difficult an...
详细信息
ISBN:
(纸本)3540400567
Most approaches to interface synthesis take two interface FSMs including transactions or burst, derive a product FSM and generate an interface circuit from the product FSM. Withthese methods, it could be difficult and complicated to describe interface FSM of IP especially when IP has many transactions. Additionally, such descriptions may lead to a very large product FSM which results in large interface circuits. We propose a simplified interface FSM description scheme where transactions are represented based on transfers and several parameters. Since all transactions supported by IP may not be used in the system, the synthesis algorithm is designed to consider only those transactions which are involved in parameter matching. through experiments we observed that our description scheme helps reduce the size of interface circuits and our synthesis method correctly generates the interface circuits.
While bypassing algorithms have been applied to the first-level cache, we study for the first time their effectiveness for the last-level caches for which miss penalties are significantly higher and where algorithm co...
详细信息
ISBN:
(纸本)3540400567
While bypassing algorithms have been applied to the first-level cache, we study for the first time their effectiveness for the last-level caches for which miss penalties are significantly higher and where algorithm complexity is not constrained by the speed of the pipeline. Our algorithm monitors the reuse behavior of blocks that are touched by delinquent loads and re-classify them on-the-fly. Blocks classified as bypassed are only installed in the level-1 cache. We leverage the algorithm to early send out a miss request for loads expected to request blocks classified to be bypassed. Such requests are sent to memory directly without tag checks at intermediary levels in the cache hierarchy. Overall, we find that we can robustly reduce the miss rate by 23% and improve IPC with 14% on average for memory bound SPEC2000 applications without degrading performance of the other SPEC2000 applications.
暂无评论