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检索条件"任意字段=10th IFIP International Conference on Network and Parallel Computing, NPC 2013"

共 71 条记录，以下是31-40 订阅

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Roadside Infrastructure Placement for Information Dissemination in Urban ITS Based on a Probabilistic Model

Roadside Infrastructure Placement for Information Disseminat...

引用

10th ifip international conference on network and parallel computing (npc)

作者： Xie, Bo Xia, Geming Chen, Yingwen Xu, Ming Natl Univ Def Technol Comp Sch Dept Network Engn Changsha Hunan Peoples R China

ISBN: (纸本)9783642408199;9783642408205

Information dissemination is an important application in VANETs for traffic safety and efficiency. In urban area, roadside infrastructure nodes can be deployed for information dissemination. However, it is inefficient and uneconomical to cover the whole urban area. How to find the optimal locations to place DPs is a research problem. Some works on this issue have to collect accurate trajectories of all the vehicles, which is not practical in the real environment. In this paper, we propose a novel approach for DPs placement in grid road networks without knowing trajectories. Based on the analysis of path number between two intersections, a probabilistic model is proposed to get the trajectories estimation of vehicles. the theoretical optimal algorithm (OA) and two heuristic algorithms (called KP-G and GA) are developed for the problem. Simulation results reveal that GA is scalable and has the highest coverage ratio on average.

关键词： Roadsides

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Total Exchange Routing on Hierarchical Dual-Nets

Total Exchange Routing on Hierarchical Dual-Nets

引用

10th ifip international conference on network and parallel computing (npc)

作者： Li, Yamin Chu, Wanming Hosei Univ Tokyo 1848584 Japan Univ Aizu Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9783642408199;9783642408205

the hierarchical dual-net (HDN) is a newly proposed interconnection network for massive parallel computers. the HDN is constructed based on a symmetric product graph (base network). A k-level hierarchical dual-net, HDN(B, k, S), contains n(k) = (2n(0))(2k) /(2 Pi(k)(i=1) s(i)) nodes, where S = {G(1)', G(2)', ... , G(k)'}, G(i)' is a super-node and s(i) = vertical bar G(i)'vertical bar is the number of nodes in the super-node at the level i for 1 <= i <= k, and n(0) is the number of nodes in the base network B. the S is used mainly for adjusting the scale of the system. the node degree of HDN(B, k, S) is d(0) + k, where d(0) is the node degree of the base network. the HDN is node and edge symmetric and can contain huge number of nodes with small node-degree and short diameter. the total exchange is one of the most dense communication patterns and is at the heart of numerous applications and programming models in parallel computing. In this paper, we show that the total exchange routing can be done on HDN efficiently.

关键词： interconnection network total exchange routing

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A Fine-Grained Pipelined Implementation of LU Decomposition on SIMD Processors

A Fine-Grained Pipelined Implementation of LU Decomposition ...

引用

10th ifip international conference on network and parallel computing (npc)

作者： Zhang, Kai Chen, ShuMing Liu, Wei Ning, Xi Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9783642408199;9783642408205

the LU decomposition is a widely used method to solve the dense linear algebra in many scientific computation applications. In recent years, the single instruction multiple data (SIMD) technology has been a popular method to accelerate the LU decomposition. However, the pipeline parallelism and memory bandwidth utilization are low when the LU decomposition mapped onto SIMD processors. this paper proposes a fine-grained pipelined implementation of LU decomposition on SIMD processors. the fine-grained algorithm well utilizes data dependences of the native algorithm to explore the fine-grained parallelism among all the computation resources. By transforming the non-coalesced memory access to coalesced version, the proposed algorithm can achieve the high pipeline parallelism and the high efficient memory access. Experimental results show that the proposed technology can achieve a speedup of 1.04x to 1.82x over the native algorithm and can achieve about 89% of the peak performance on the SIMD processor.

关键词： parallel processing systems

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Energy Efficient Task Scheduling in Mobile Cloud computing

Energy Efficient Task Scheduling in Mobile Cloud Computing

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10th ifip international conference on network and parallel computing (npc)

作者： Yao, Dezhong Yu, Chen Jin, Hai Zhou, Jiehan Huazhong Univ Sci & Technol Sch Comp Sci & Technol Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Peoples R China Univ Oulu Dept Comp Sci & Engn Oulu 90014 Finland

ISBN: (纸本)9783642408199;9783642408205

Cloud computing can enhance the computing capability of mobile systems by offloading. However, the communication between the mobile device and the cloud is not free. Transmitting large data to cloud consumes much more energy than processing data in mobile device, especially in a low bandwidth condition. Further, some processing tasks can avoid transmitting large data between mobile device and server. those processing tasks (encoding, rendering) are as the compress algorithm, which can reduce the size of raw data before it is sent to server. In this paper, we present an energy efficient task scheduling strategy (EETS) to determine what kind of task with certain amount of data should be chosen to be offloaded under different environment. We have evaluated the scheduler by using an Android smartphone. the results show that our strategy can achieve 99% of accuracy to choose the right action in order to minimize the system energy usage.

关键词： Mobile cloud computing Energy-efficient Task scheduling Offloading

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Accelerating parallel Frequent Itemset Mining on Graphics Processors with Sorting

Accelerating Parallel Frequent Itemset Mining on Graphics Pr...

引用

10th ifip international conference on network and parallel computing (npc)

作者： Huang, Yuan-Shao Yu, Kun-Ming Zhou, Li-Wei Hsu, Ching-Hsien Liu, Sheng-Hui Chung Hua Univ Dept Comp Sci & Informat Engn Hsinchu Taiwan Harbin Univ Sci & Technol Sch Software Heilongjiang Peoples R China

ISBN: (纸本)9783642408199;9783642408205

Frequent Itemset Mining (FIM) is one of the most investigated fields of data mining. the goal of Frequent Itemset Mining (FIM) is to find the most frequently-occurring subsets from the transactions within a database. Many methods have been proposed to solve this problem, and the Apriori algorithm is one of the best known methods for frequent Itemset mining (FIM) in a transactional database. In this paper, a parallel Frequent Itemset Mining Algorithm, called Accelerating parallel Frequent Itemset Mining on Graphic Processors with Sorting (APFMS), is presented. this algorithm utilizes new-generation graphic processing units (GPUs) to accelerate the mining process. In it, massive processing units of GPU were used to speed up the frequent item verification procedure on the OpenCL platform. the experimental results demonstrated that the proposed algorithm had dramatically reduced computation time compared with previous methods.

关键词： parallel Data Mining Apriori Graphic Processing Unit (GPU)

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BotInfer: A Bot Inference Approach by Correlating Host and network Information

BotInfer: A Bot Inference Approach by Correlating Host and N...

引用

10th ifip international conference on network and parallel computing (npc)

作者： He, Yukun Li, Qiang Ji, Yuede Guo, Dong Jilin Univ Coll Comp Sci & Technol Changchun 130012 Peoples R China

ISBN: (纸本)9783642408199;9783642408205

Botnet is widely used in cyber-attacks and becomes a serious threat to network security. Existing approaches can detect botnet effectively in certain environments, however problems still exist in using host or network detection approaches respectively, such as robustness in detection tools, difficulties in global deployment and low precision rate. To solve the above problems, a novel detection approach called BotInfer is proposed. In BotInfer approach, host-based bot detection tools are deployed on some of the hosts;network flow of all the hosts is captured and analyzed;host detection result and flow information are correlated by the bot inference engine. through the experiments, BotInfer can effectively detect the hosts in the network. When the deployment rate of bot detection tools in the network reaches 80%, the precision rate of the hosts with detection tools is about 99%, and the precision rate of the hosts without detection tools is about 86%.

关键词： bot detection cluster flow analysis inference algorithm

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Software/Hardware Hybrid network-on-Chip Simulation on FPGA

Software/Hardware Hybrid Network-on-Chip Simulation on FPGA

引用

10th ifip international conference on network and parallel computing (npc)

作者： Zhang, Youhui Qu, Peng Qian, Ziqiang Wang, Hongwei Zheng, Weimin Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9783642408199;9783642408205

In this paper, a software-and-hardware hybrid simulation method for CMP (Chip-MultiProcessor) system is designed, as well as its performance model. In detail, the NoC (network-On-Chip) module is totally simulated by the FPGA resource;a software-and-hardware interaction interface of this module is provided so that the simulation software running on the on-chip soft core can cooperate with the NoC to complete the whole simulation. In other words, the most time-consuming and relatively-fixed part is implemented by hardware and others are implemented by software, which maintains simulation flexibility and high performance owing to the compact on-chip design. We implement this design on the Xilinx's Virtex 5 155T chip and the work frequency is 100Mhz. Compared with a typical software counterpart, the simulation speed of NoC is more than 3000 times faster;and the advantage is widened further with the increasing injection rate. Moreover, compared with another hybrid method executing the software part on the host CPU, it is still fairly faster although the host performance is much higher than the on-chip core.

关键词： network on chip FPGA Simulation

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A Virtual network Embedding Algorithm Based on Graph theory

A Virtual Network Embedding Algorithm Based on Graph Theory

引用

10th ifip international conference on network and parallel computing (npc)

作者： Sun, Zhenxi Bai, Yuebin Wang, Songyang Cao, Yang Xu, Shubin Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China Sci & Technol Informat Transmiss & Disseminat Com Shijiazhuang Peoples R China Beijing Univ Posts & Telecommun Sch Comp Sci Beijing 100876 Peoples R China

ISBN: (纸本)9783642408199;9783642408205

network virtualization is becoming a promising way of removing the inherent ossification of the Internet, and has been steadily attracting more and more researchers' attention during the decades. the major challenges in this field are improving the efficiency of virtual network embedding procedure and raising the rate of virtual network requests being successfully accepted by the substrate network. this paper introduces a new virtual network embedding algorithm based on node similarity, which means the similarity between the virtual nodes and the substrate nodes. For more details, by calculating the degree of nodes both in virtual network and substrate network, which is actually the number of links associated with them, the algorithm achieves better mapping results between virtual network and the substrate network on the topology aspect.

关键词： Virtual network VN Embedding Graph theory Node Similarity

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Totoro: A Scalable and Fault-Tolerant Data Center network by Using Backup Port

Totoro: A Scalable and Fault-Tolerant Data Center Network by...

引用

10th ifip international conference on network and parallel computing (npc)

作者： Xie, Junjie Deng, Yuhui Zhou, Ke Jinan Univ Dept Comp Sci Guangzhou 510632 Guangdong Peoples R China Chinese Acad Sci State Key Lab Comp Architecture Inst Comp Technol Beijing 100190 Peoples R China Huazhong Univ Sci & Technol Minist Educ China Key Lab Data Storage Syst Sch Comp Sci & Technol Huazhong Peoples R China

ISBN: (纸本)9783642408199;9783642408205

Scalability and fault tolerance become a fundamental challenge of data center network structure due to the explosive growth of data. Both structures proposed in the area of parallel computing and structures based on tree hierarchy are not able to satisfy these two demands. In this paper, we propose Totoro, a scalable and fault-tolerant network to handle the challenges by using backup built-in Ethernet ports. We connect a bunch of servers to an intra-switch to form a basic partition. then we utilize half of backup ports to connect those basic partitions with inter-switches to build a larger partition. Totoro is hierarchically and recursively defined and the high-level Totoro is constructed by many low-level Totoros. Totoro can scale to millions of nodes. We also design a fault-tolerant routing protocol. Its capability is very close to the performance bound. Our experiments show that Totoro is a viable interconnection structure for data centers.

关键词： Data Center Interconnection network Scalability Fault Tolerance Backup Port

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Efficiency of Flexible Rerouting Scheme for Maximizing Logical Arrays

Efficiency of Flexible Rerouting Scheme for Maximizing Logic...

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10th ifip international conference on network and parallel computing (npc)

作者： Jiang, Guiyuan Wu, Jigang Sun, Jizhou Tianjin Univ Sch Comp Sci & Technol Tianjin 300072 Peoples R China Tianjin Polytech Univ Sch Comp Sci & Software Engn Tianjin 300387 Peoples R China

ISBN: (纸本)9783642408199;9783642408205

In a multiprocessor array, some processing elements (PEs) fail to function normally due to hardware defects or soft faults caused by overheating, overload or occupancy by other running applications. Fault-tolerant reconfiguration considered in this paper is to reorganize fault-free PEs from a processor array with faults to a logical array of regular mesh topology by changing the interconnections among PEs. this paper presents the efficiency of the flexible rerouting scheme to maximize the usage of the fault-free PEs, by developing an efficient reconfiguration algorithm without backtracking. the proposed algorithm constructs each logical columns from left to right on candidate PE sets. It updates the candidate sets by excluding the PEs which cannot be used, once a logical column is formed. Also, it is proved that the proposed heuristic algorithm is able to generate the maximum-size logical array in linear time. Experimental results show that 123 logical columns can be constructed on 256 x 256 host arrays with fault density of 30%, resulting in an improvement of 51% in comparison to the previous algorithm by which only 82 logical columns can be produced. Furthermore, our algorithm is able to generate target arrays with harvest over 56% on host arrays with fault density of 50%, while the previous work cited in this paper fails to construct any target array in this case.

关键词： Interconnection network reconfiguration rerouting scheme fault tolerant algorithm

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