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parallel aware hybrid Solid-State storage 15th

Parallel aware hybrid Solid-State storage

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： He, Dan Wang, Fang Feng, Dan Liu, Jingning Wu, Yunxiang He, Ying Hu, Yang Wuhan National Laboratory for Optoelectronics School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Nanchang Hangkong University Nanchang330063 China China Ship Development and Design Center Wuhan430064 China

ISBN: (纸本)9783319271392

Compared with tradition disk, NAND Flash has advantages of higher performance and shock resistance. But before write, NAND Flash must erase the old messages. that why NAND Flash based Solid State Disks (SSDs) always use the log-based schemes to improve the performance. Compared with NAND Flash, Phase Change Memory (PCM) has higher write performance, longer lifetime, and can update in-place, but its cost is high and capacity is low. So, in PCM and NAND Flash hybrid SSD, PCM is always used as log region, such as In-Page Logging-based (hybrid-IPL) SSD. the log-based SSD incurs a large number of merge operations. the cost of merge operation is very high because it involves many read, write operations, as well as an erase operation. So, how to reduce the cost of merge operations is the critical challenge to log-based hybrid (PCM and flash) SSD. In this paper, we propose a new merge scheme in PCM and NAND Flash hybrid SSD, called parallel aware hybrid In-Page Logging-based (P-aware-IPL) SSD. this scheme can exploit the die-level and plane-level parallelism of flash. Leveraging these two levels of parallelism, the cost of full merge is significantly reduced compared with that of hybrid-IPL SSD scheme and there is no other additional overhead in our algorithm. Experiment results have shown that the proposed P-aware-IPL reduces the flash write and erase operations by up to 10% and average response time by up to 22% against the hybrid-IPL scheme. © Springer international Publishing Switzerland 2015.

关键词： Cost reduction

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A Hierarchical Model for the Analysis of Efficiency and Speed-Up of Multi-core Cluster-Computers

A Hierarchical Model for the Analysis of Efficiency and Spee...

引用

international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Heinz Kredel Hans Günther Kruse Sabine Richling IT-Center University of Mannheim Germany IT-Center University of Heidelberg Germany

We develop a simple hierarchical model for the performance analysis of compute clusters assembled from multi-core compute nodes connected by a (high-speed) network. the performance is described by the dimensionless speed-up and efficiency in dependence on important hardware and application parameters. the hardware parameters are the number of compute nodes and the bandwidth the network, together with the number of cores per node, the theoretical performance of each core and the bandwidth of the main memory. the application parameters are the total number of operations performed on a number of bytes and the total number of bytes communicated between the processing units. In order to exemplify our concept we apply it to the scalar product of vectors, matrix multiplication, Linpack and FFT. Our previous performance models are contained as special cases in the new more comprehensive approach.

关键词： Computational modeling Mathematical model Bandwidth Analytical models Hardware Computers Multicore processing

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Spatial data processing with MapReduce

Spatial data processing with MapReduce

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international conference on Industrial and Information Systems, ICIIS

作者： Tilani Gunawardena Annamaria Vicari Giansalvatore Mecca Department of Mathematics Computer Science and Economics University Of Basilicata Potenza Italy National Institute of Geophysics and Volcanology Italy

the current development of high performance parallel supercomputing infrastructures are pushing the boundaries of applications of science and are bringing new paradigms into engineering practices and simulations. Earthquake engineering is also one of the major fields, which benefits from above by looking for solutions in grid computing and cloud computing techniques. Generally, earthquake simulations involve analysis of petabytes of data. Analyzing these large amounts of data in parallel in thousands of nodes in computer clusters results in gaining high performances. Open source cloud solutions such as Hadoop MapReduce, which is highly scalable and capable of processing large amount of data rapidly in parallel on large clusters provide better solution compared to RDBDM. Both GPUs and MapReduce are designed to support vast data parallelism. For performance considerations, GPU computing could be adopted over low performing CPU systems. this paper discusses MapReduce system using Hadoop and Mars. Mars is a MapReduce framework on graphics processor. Hence, the proposition is to use GPU based systems for earthquake simulations in which Digital elevation model 3D data sets are fully materialized where scientist can make use of these data for various analysis and simulations.

关键词： Graphics processing units Feeds Mars

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Program slicing based on runtime dataflow measurements

Program slicing based on runtime dataflow measurements

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international Carpathian Control conference (ICCC)

作者： Gábor Wacha János Lazányi Béla Fehér Department of Measurement and Information Technology Budapest University of Technology and Economics Budapest Hungary

Multicore architectures enable increasing the performance of the system with parallel processing. One of the challenges of a multicore embedded system is the correct usage of the processor cores. It is possible to achieve balanced processor load on the different cores, but the communication bandwidth between the cores is often a bottleneck. Passing large amounts of data between tasks mapped to different processor cores can result in cache misses in the local cache of a processor core. this paper introduces an analyzation method based on runtime generated data flow graphs to find the data paths of an algorithm. It shows that a spectral cluster analysis can help to discover data independent subsets in the algorithm under test. Finding the data independent parts helps to partition the program to multiple slices where the inter-slice communication is kept as low as possible. With our proposed method the communication bottleneck can be evaded in a multicore, multitask implementation, possibly resulting in better performance.

关键词： Multicore processing Clustering algorithms Algorithm design and analysis Software Runtime Software algorithms Symmetric matrices

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Completion time-a ware flow scheduling in heterogenous networks 1

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15th international conference on algorithms and architectures for parallel processing, ICA3PP 2015

作者： He, Shiming Xie, Kun Zhang, Dafang Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation School of Computer and Communication Engineering Hunan Province Engineering Research Center of Electric Transportation and Smart Distributed Network Changsha University of Science and Technology Changsha410114 China College of Computer Science and Electronics Engineering Hunan University Changsha410082 China Department of Electrical and Computer Engineering State University of New York at Stony Brook NY United States

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

In China, the expressway isn’t free. When a vehicle exits, the exit toll station needs to calculate the toll according to the vehicle trajectory obtained by sending a trajectory query task to the trajectory center remotely. For the accurate of toll and keep the exit smoothly, transmitting the trajectory result reliably and in time is a key issue. there are three heterogenous networks in expressway, Fibernet, Telecommunications Network and 3G. We concurrently exploit three heterogenous networks by allocating the trajectory result into three sub-flows where each sub-flow is transmitted in one kind of networks. But existing multipath transfer solution(FMTCP) doesn’t consider the difference of completed time among all sub-flows and can’t make sure the completed time in time. therefore, we formulate the sub-flows schedule as a integer programming problem, which is proved to be NP-hard problem, and propose a Completion time-aware Flow Scheduling scheme (CaFS) which calculates the size of sub-flows. For the reliably, it exploits generation-based network coding. For the transmission in time, CaFS allocates the size of sub-flow into suitable generation and scheduling the generations. the simulation results demonstrate that, comparing with the FMTCP, CaFS improves 31. 9% in completion time and 30% in task finished rate. © Springer international Publishing Switzerland 2015.

关键词： Network coding

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Anonymous Communication in the Browser via Onion-Routing

Anonymous Communication in the Browser via Onion-Routing

引用

international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Florian Burgstaller Andreas Derler Stefan Kern Gabriel Schanner Andreas Reiter Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology Austria

Every single communication on the Internet reveals private and sensitive information of the communicating parties if no further measures are applied. Various applications and measures are already available to e.g. tunnel traffic through other nodes to obscure the original sender and receiver. Existing frameworks require external applications, running on the particular nodes. We propose a flexible architecture for an anonymous communication framework that supports the interoperability among different platforms. Our proof-of-concept implementation, based on web standards and web technologies shows the feasibility of the framework in terms of usability and interoperability. the framework is running completely in the web-browser and does not have requirements on external applications. the evaluation results show that our framework brings great benefits to user's privacy and security.

关键词： Peer-to-peer computing Browsers WebRTC Servers Public key Protocols

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Accelerating Physical Simulations from a Multicomponent Lattice Boltzmann Method on a Single-Node Multi-GPU Architecture

Accelerating Physical Simulations from a Multicomponent Latt...

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international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Julien Duchateau François Rousselle Nicolas Maquignon Gilles Roussel Christophe Renaud Laboratoire d'Informatique Signal Image de la Côte d'Opale Université du Littoral Côte d'Opale Calais France

In this paper, we introduce an efficient method to accelerate flow simulations for an isothermal multiphase and multicomponent (MPMC) Lattice Boltzmann method (LBM) on a single-node multi-GPU architecture. Our objective is to propose an efficient way to improve performance of multiphase and multicomponent Lattice Boltzmann simulations by the use of Nvidia GPUDirect technology and Peer-to-Peer (P2P) data transfers. Optimization of Peer-to-Peer communications is also studied in this work by the use of a clustering algorithm. Several simulations are shown and performance is discussed in order to validate the method.

关键词： Computational modeling Peer-to-peer computing Lattice Boltzmann methods Graphics processing units Mathematical model Data models Data transfer

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parallel applications and on-chip traffic distributions: Observation, implication and modelling

Parallel applications and on-chip traffic distributions: Obs...

引用

international Joint conference on Software Technologies (ICSOFT)

作者： thomas Canhao Xu Jonne Pohjankukka Paavo Nevalainen Tapio Pahikkala Ville Leppänen Department of Information Technology University of Turku Turku Finland

ISBN: (纸本)9781467385312

We study the traffic characteristics of parallel and high performance computing applications in this paper. Applications that utilize multiple cores are more and more common nowadays due to the emergence of multicore processors. However the design nature of single-threaded applications and multi-threaded applications can vary significantly. Furthermore the on-chip communication profile of multicore systems should be analysed and modelled for characterization and simulation purposes. We investigate several applications running on a full system simulation environment. the on-chip communication traces are gathered and analysed. We study the detailed low-level profiles of these applications. the applications are categorized into different groups according to various parallel programming paradigms. We discover that the trace data follow different parameters of power-law model. the problem is solved by applying least-squares linear regression. We propose a generic synthetic traffic model based on the analysis results.

关键词： Multicore processing Program processors System-on-chip Analytical models Data models Protocols Computational modeling

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Massive efficiencies to be realized through GPU computations in finite element optimization: the promises and observations

Massive efficiencies to be realized through GPU computations...

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international conference on Industrial and Information Systems, ICIIS

作者： S. Ratnajeevan H. Hoole Election Commission Sarana Mawatha Rajagiriya 10107 Sri Lanka

In finite element optimization, the computational load limits the size of problem that can be solved. Finite element computation involves the solution of large matrix equations. then optimization requires several such equations to be solved. parallelization has been the preferred route to overcome this problem but was again limited by the cost of computers and the number of processors available. the graphics processing unit (GPU) on a PC provides a means of implementing the massive computations on numerous parallel threads cheaply on PCs. the purpose of this is to review finite element matrix equation solution on the GPU and point out areas where further investigation is warranted. Our intention is to direct computational research and computer architecture development so that we may use the GPU better for more effective computational parallelization in finite element field computation.

关键词： Graphics processing units Finite element analysis Refining Acceleration

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FPGA-based Acceleration of Deep Neural Networks Using High Level Method

FPGA-based Acceleration of Deep Neural Networks Using High L...

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international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Lei Liu Jianlu Luo Xiaoyan Deng Sikun Li Department of Electronics Officers College Of Chinese Armed Police Force Cheng Du China School of Computer Science National University of Defense Technology Chang Sha China

ISBN: (纸本)9781467394741

Deep neural network (DNN) is becoming more and more applied in data center applications such as speech recognition, image search, etc. However, the training in DNN is very time-consuming because of its deep structure. this paper presents FPGA-based acceleration of deep neural networks using a high level method and proposes a parallel optimizing strategy using the Kintex-7 FPGA board's features. Experimental results show that it can increase the utilization of FPGA computation units with low mini-batch size and reduce the transfer cost effectively. the optimized algorithm achieves up to 17.65x higher performance than CPU.

关键词： Training Field programmable gate arrays Acceleration Speech recognition Graphics processing units Biological neural networks

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