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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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23rd international conference on Software Engineering and Data Engineering, SEDE 2014

23rd International Conference on Software Engineering and Da...

引用

2014 10th IEEE international conference on Intelligent Computer Communication and processing, ICCP 2014

ISBN: (纸本)9781479965687

the proceedings contain 61 papers. the topics discussed include: multi-objective hardware-software co-optimization for the SNIPER multi-core simulator;consistency checking of safety arguments in the goal structuring notation standard;interleaving ontology-based reasoning and natural language processing for character identification in folktales;nonparametric weighted MMC feature extraction method for HRRP recognition;real-time pedestrian detection in urban scenarios;vision algorithms and embedded solution for pedestrian detection with far infrared camera;aggregate road surface based environment representation using digital elevation maps;UDCT complex coefficient statistics based rotation invariant texture characterization;industrial AGVs: toward a pervasive diffusion in modern factory warehouses;protecting cache memories through data scrambling technique;parallel object-oriented implementation of the TestU01 statistical test suites;and parallel implementation of the matrix rank test for randomness assessment.

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Many-core applications to online track reconstruction in HEP experiments

Many-core applications to online track reconstruction in HEP...

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20th international conference on Computing in High Energy and Nuclear Physics (CHEP)

作者： Amerio, S. Bastieri, D. Corvo, M. Gianelle, A. Ketchum, W. Liu, T. Lonardo, A. Lucchesi, D. Poprocki, S. Rivera, R. Tosoratto, L. Vicini, P. Wittich, P. Ist Nazl Fis Nucl Padua Italy Univ Padua Padua Italy Los Alamos Natl Lab Los Alamos NM 87544 USA Fermilab Natl Accelerator Lab Batavia IL 60510 USA INFN Roma Rome Italy Cornell Univ Ithaca NY 14850 USA

Interest in parallel architectures applied to real time selections is growing in High Energy Physics (HEP) experiments. In this paper we describe performance measurements of Graphic processing Units (CPUs) and Intel Many Integrated Core architecture (MIC) when applied to a typical HEP online task: the selection of events based on the trajectories of charged particles. We use as benchmark a scaled-up version of the algorithm used at CDF experiment at Tevatron for online track reconstruction - the SVT algorithm - as a realistic test-case for low-latency trigger systems using new computing architectures for LHC experiment. We examine the complexity/performance trade-off in porting existing serial algorithms to many-core devices. Measurements of both data processing and data transfer latency are shown, considering different I/O strategies to/from the parallel devices.

关键词： parallel architectures

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Resolving Load Balancing Issues in BWA on NUMA Multicore architectures 1

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10th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Herzeel, Charlotte Ashby, thomas J. Costanza, Pascal De Meuter, Wolfgang IMEC B-3001 Louvain Belgium

ISBN: (数字)9783642551956

ISBN: (纸本)9783642551956

Running BWA in multithreaded mode on a multi-socket server results in poor scaling behaviour. this is because the current parallelisation strategy does not take into account the load imbalance that is inherent to the properties of the data being aligned, e.g. varying read lengths and numbers of mutations. Additional load imbalance is also caused by the BWA code not anticipating certain hardware characteristics of multi- socket multicores, such as the non-uniform memory access time of the different cores. We show that rewriting the parallel section using Cilk removes the load imbalance, resulting in a factor two performance improvement over the original BWA.

关键词： BWA Multithreading NUMA Load balancing Cilk

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An improved simulated annealing heuristic for static partitioning of task graphs onto heterogeneous architectures 20

An improved simulated annealing heuristic for static partiti...

引用

20th IEEE international conference on parallel and Distributed Systems (ICPADS)

作者： Vasudevan, Aravind Malik, Avinash Gregg, David Trinity Coll Dublin Sch Comp Sci & Stat Dublin Ireland Univ Auckland Auckland 1 New Zealand

ISBN: (纸本)9781479976157

We present a simulated annealing based partitioning technique for mapping task graphs, onto heterogeneous processing architectures. Task partitioning onto homogeneous architectures to minimize the makespan of a task graph, is a known NP-hard problem. Heterogeneity greatly complicates the aforementioned partitioning problem, thus making heuristic solutions essential. A number of heuristic approaches have been proposed, some using simulated annealing. We propose a simulated annealing method with a novel NEXT STATE function to enable exploration of different regions of the global search space when the annealing temperature is high and making the search more local as the temperature drops. the novelty of our approach is two fold: (1) we go a step further than the existing scientific literature, considering heterogeneity at levels of task parallelism, data parallelism and communication. (2) We present a novel algorithm that uses simulated annealing to find better partitions in the presence of heterogeneous architectures, data parallel execution units, and significant data communication costs. We conduct a statistical analysis of the performance of the proposed method, which shows that our approach clearly outperforms the existing simulated annealing method.

关键词： Simulated annealing

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Cognitive information processing based on a parallel processor

Cognitive information processing based on a parallel process...

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10th international conference on Digital Technologies

作者： Verenik, Nikolai L. Girel, Alexey I. Seitkulov, Yerzhan N. Tatur, Mikhail M. Razhkova, Hanna P. Belarusian State Univ Informat & Radioelect Minsk BELARUS LN Gumilyov Eurasian Natl Univ Astana Kazakhstan Intellectual Proc Ltd Minsk BELARUS

ISBN: (纸本)9781479933037

In this paper we consider the cognitive process as a set of different tasks. In particular tasks of clustering, classification and search of association. Described the parameters of similarity of these tasks, hypothesized the possibility of creating a unified methodology for cognitive systems. Shown the possible original architecture of the system, its description, command and data formats, the principles of operation. Describes the implementation of a system model for the GPU.

关键词： concurrent processor Information processing Religious Missions cognitive function cognitive process Automatic data processing Building systems Systems modelling data formats

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Scheduling Moldable Tasks with Precedence Constraints and Arbitrary Speedup Functions on Multiprocessors 1

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10th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Hunold, Sascha Vienna Univ Technol Res Grp Parallel Comp A-1040 Vienna Austria

ISBN: (数字)9783642551956

ISBN: (纸本)9783642551956

Due to the increasing number of cores of current parallel machines, the question arises to which cores parallel tasks should be mapped. thus, parallel task scheduling is now more relevant than ever, especially under the moldable task model, in which tasks are allocated a fixed number of processors before execution. Scheduling algorithms commonly assume that the speedup function of moldable tasks is either non-decreasing, sub-linear or concave. In practice, however, the resulting speedup of parallel programs on current hardware with deep memory hierarchies is most often neither non-decreasing nor concave. We present a new algorithm for the problem of scheduling moldable tasks with precedence constraints for the makespan objective and for arbitrary speedup functions. We show through simulation that the algorithm not only creates competitive schedules for moldable tasks with arbitrary speedup functions, but also outperforms other published heuristics and approximation algorithms for non-decreasing speedup functions.

关键词： Multiprocessor scheduling Homogeneous processors Moldable tasks Makespan optimization Speedup functions

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Exploiting Data Sparsity in parallel Matrix Powers Computations

Exploiting Data Sparsity in Parallel Matrix Powers Computati...

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10th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Knight, Nicholas Carson, Erin Demmel, James Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9783642552243

We derive a new parallel communication-avoiding matrix powers algorithm for matrices of the form A = D + USVH, where D is sparse and USVH has low rank and is possibly dense. We demonstrate that, with respect to the cost of computing k sparse matrix-vector multiplications, our algorithm asymptotically reduces the parallel latency by a factor of O(k) for small additional bandwidth and computation costs. Using problems from real-world applications, our performance model predicts up to 13x speedups on petascale machines.

关键词： Communication-avoiding Matrix powers Graph cover Hierarchical matrices parallel algorithms

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Document clustering using multi-objective genetic algorithms with parallel programming based on CUDA 11

Document clustering using multi-objective genetic algorithms...

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11th international conference on Informatics in Control, Automation and Robotics, ICINCO 2014

作者： Lee, Jung Song Park, Soon Cheol Lee, Jong Joo Ham, Han Heeh Division of Electronics and Information Engineering Chonbuk National University Jeonju-si Korea Republic of Department of Korean Language and Literature Chonbuk National University Jeonju-si Korea Republic of Department of Archeology and Cultural Anthropology Chonbuk National University Jeonju-si Korea Republic of

ISBN: (纸本)9789897580390

In this paper, we propose a method of enhancing Multi-Objective Genetic algorithms (MOGAs) for document clustering with parallel programming. the document clustering using MOGAs shows better performance than other clustering algorithms. However, the overall computation time of the MOGAs is considerably long as the number of documents increases. To effectively avoid this problem, we implement the MO-GAs with General-Purpose computing on Graphics processing Units (GPGPU) to compute the document similarities for the clustering. Furthermore, we introduce two thread architectures (Term-threads and Document-threads) in the CUDA (Compute Unified Device Architecture) language. the experimental results show that the parallel MOGAs with CUDA are tremendously faster than the general MOGAs.

关键词： Graphics processing unit

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A GPU Implementation of Clipping-Free Halftoning Using the Direct Binary Search 1

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14th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Koge, Hiroaki Ito, Yasuaki Nakano, Koji Hiroshima Univ Dept Informat Engn Higashihiroshima 7398527 Japan

ISBN: (数字)9783319111971

ISBN: (纸本)9783319111971;9783319111964

Halftoning is an important process to convert a gray scale image into a binary image with black and white pixels. the clipping-free DBS (Direct Binary Search)-based halftoning is one of the halftoning methods that can generate high quality binary images. However, considering the computing time, it is not realistic for most applications such as printing purpose. the main contribution of this paper is to show a new GPU implementation for the clipping-free DBS-based halftoning. We have considered programming issues of the GPU architecture to implement the method on the GPU. the experimental result shows that our GPU implementation on NVIDIA GeForce GTX 780 Ti for a 4096x3072 gray scale image runs in 7.240 seconds, while the CPU implementation runs in 346.6 seconds. thus, our GPU implementation attains a speed-up factor of 47.82.

关键词： Image processing Halftoning Direct binary search Clipping-free GPGPU

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Adaptive parallel Compressed Event Matching

Adaptive Parallel Compressed Event Matching

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IEEE 30th international conference on Data Engineering (ICDE)

作者： Sadoghi, Mohammad Jacobsen, Hans-Arno IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA Univ Toronto Middleware Syst Res Grp Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781479934805

the efficient processing of large collections of patterns expressed as Boolean expressions over event streams plays a central role in major data intensive applications ranging from user-centric processing and personalization to real-time data analysis. On the one hand, emerging user-centric applications, including computational advertising and selective information dissemination, demand determining and presenting to an end-user the relevant content as it is published. On the other hand, applications in real-time data analysis, including push-based multi-query optimization, computational finance and intrusion detection, demand meeting stringent subsecond processing requirements and providing high-frequency event processing. We achieve these event processing requirements by exploiting the shift towards multi-core architectures by proposing novel adaptive parallel compressed event matching algorithm (A-PCM) and online event stream re-ordering technique (OSR) that unleash an unprecedented degree of parallelism amenable for highly parallel event processing. In our comprehensive evaluation, we demonstrate the efficiency of our proposed techniques. We show that the adaptive parallel compressed event matching algorithm can sustain an event rate of up to 233,863 events/second while state-of-the-art sequential event matching algorithms sustains only 36 events/second when processing up to five million Boolean expressions.

关键词： Data analysis Encoding Indexes Instruction sets Phase change materials Real-time systems Subscriptions

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