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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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parallel Image Texture Feature Extraction under Hadoop Cloud Platform

Parallel Image Texture Feature Extraction under Hadoop Cloud...

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10th international conference on Intelligent Computing (ICIC)

作者： Zhu, Hao-Dong Shen, Zhen Shang, Li Zhang, Xiao-Ping ZhengZhou Univ Light Ind Sch Comp & Commun Engn Zhengzhou 450002 Henan Peoples R China Suzhou Vocat Univ Dept Commun Technol Coll Elect Informat Engn Suzhou Peoples R China Tongji Univ Shanghai Coll Elect & Informat Engn Shanghai Peoples R China

ISBN: (纸本)9783319093338;9783319093321

With the increasing amount of digital image data, massive image process and feature extraction process have become a time-consuming process. As an excellent mass data processing and storage capacity of the open source cloud platform, Hadoop provides a parallel computing model MapReduce, HDFS distributed file system module. Firstly, we introduced Hadoop platform programming framework and Tamura texture features. And then, the image processing and feature texture feature extraction calculations involved in the process to achieve Hadoop platform. the results which comparison with Matlab platform shows it is less obvious advantage of Hadoop platform in image processing and feature extraction of lower-resolution images, but for image processing and feature extraction of high-resolution images, the time spent in Hadoop platform is greatly reducing, data processing capability the advantages is obvious.

关键词： Hadoop Tamura Texture Feature Image processing Feature Extraction

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Heterogeneity-conscious parallel query execution: Getting a better mileage while driving faster!

Heterogeneity-conscious parallel query execution: Getting a ...

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10th international Workshop on Data Management on New Hardware, DaMoN 2014 - In Conjunction with the ACM SIGMOD/PODS conference

作者： Mühlbauer, Tobias Rödiger, Wolf Seilbeck, Robert Kemper, Alfons Neumann, thomas Technische Universität München Germany

ISBN: (纸本)9781450329712

Physical and thermal restrictions hinder commensurate performance gains from the ever increasing transistor density. While multi-core scaling helped alleviate dimmed or dark silicon for some time, future processors will need to become more heterogeneous. To this end, single instruction set architecture (ISA) heterogeneous processors are a particularly interesting solution that combines multiple cores with the same ISA but asymmetric performance and power characteristics. these processors, however, are no free lunch for database systems. Mapping jobs to the core that fits best is notoriously hard for the operating system or a compiler. To achieve optimal performance and energy efficiency, heterogeneity needs to be exposed to the database system. In this paper, we provide a thorough study of parallelized core database operators and TPC-H query processing on a heterogeneous single-ISA multi-core architecture. Using these insights we design a heterogeneity-conscious job tocore mapping approach for our high-performance main memory database system HyPer and show that it is indeed possible to get a better mileage while driving faster compared to static and operating-system-controlled mappings. Our approach improves the energy delay product of a TPC-H power run by 31% and up to over 60% for specific TPC-H queries. Categories and Subject Descriptors H.2 [Database Management]: Systems. Copyright 2014 ACM.

关键词： Mapping

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Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation

Efficient and scalable CGRA-based implementation of Column-w...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Zoltán Endre Rákossy Farhad Merchant Axel Acosta-Aponte S.K. Nandy Anupam Chattopadhyay Institute for Communication Technologies and Embedded Systems (ICE) RWTH University Aachen Germany CADLab Indian Institute of Science Bangalore India

Givens Rotation is a key computation-intensive block in embedded wireless applications. In order to achieve an efficient mapping which smoothly scales to the underlying architecture, we propose two new Column-based Givens Rotation algorithms, derived from traditional Fast Givens and Square-root and Division Free Givens algorithms. these algorithms allow annihilation of multiple elements in a column of the input matrix simultaneously, without a dependency bottle-neck allowing increased parallelism, resource sharing and scalability. the ease of mapping and scalability has been tested on a layered coarse-grained reconfigurable architecture reaching close to optimal results for highly parallel architectures.

关键词： parallel processing Scalability Arrays Kernel Algorithm design and analysis Complexity theory

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Performance Analysis for Stencil-Based 3D MPDATA Algorithm on GPU Architecture

Performance Analysis for Stencil-Based 3D MPDATA Algorithm o...

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10th international conference on parallel processing and Applied Mathematics (PPAM)

作者： Rojek, Krzysztof Szustak, Lukasz Wyrzykowski, Roman Czestochowa Tech Univ PL-42201 Czestochowa Poland

ISBN: (纸本)9783642552243

EULAG (Eulerian/semi-Lagrangian fluid solver) is an established computational model for simulating thermo-fluid flows across a wide range of scales and physical scenarios. the multidimensional positive defined advection transport algorithm (MPDATA) is among the most time-consuming components of EULAG. the main aim of our work is to design an efficient adaptation of the MPDATA algorithm to the NVIDIA GPU Kepler architecture. We focus on analysis of resources usage in the GPU platform and its influence on performance results. In this paper, a performance model is proposed, which ensures a comprehensive analysis of the resource consumption including registers, shared, global and texture memories. the performance model allows us to identify bottlenecks of the algorithm, and shows directions of optimizations. the group of the most common bottlenecks is considered in this work. they include data transfers between host memory and GPU global memory, GPU global memory and shared memory, as well as latencies and serialization of instructions, and GPU occupancy. We put the emphasis on providing a fixed memory access pattern, padding, reducing divergent branches and instructions latencies, as well as organizing computation in the MPDATA algorithm in order to provide efficient shared memory and register file reusing.

关键词： GPGPU CUDA EULAG Stencil MPDATA Geophysical flows parallel programming

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Performance Analysis of parallel Sorting algorithms Using MPI

Performance Analysis of Parallel Sorting Algorithms Using MP...

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Frontiers of Information Technology (FIT)

作者： Muhammad Hanif Durad Muhammad Naveed Akhtar Irfan-ul-Haq

Sorting is one of the classic problems of data processing and many practical applications require implementation of parallel sorting algorithms. Only a few algorithms have been implemented using MPI, in this paper a few additional parallel sorting algorithms have been implemented using MPI. A unified performance analysis of all these algorithms has been presented using two different architectures. On basis of experimental results obtained some guidelines has been suggested for the selection of proper algorithms.

关键词： Sorting Algorithm design and analysis Clustering algorithms Market research Hypercubes Performance analysis

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parallel Factorization Machine Recommended Algorithm Based on MapReduce

Parallel Factorization Machine Recommended Algorithm Based o...

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international conference on Semantics, Knowledge and Grid (SKG)

作者： Hanxiao Sun Wenjie Wang Zhongzhi Shi School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing China Key Laboratory of Intelligent Information Processing Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781479967162

Factorization Machines [1, 2] is a new factorization model that can combine the merits of SVM model with matrix factorization models. It can model all the interactive actions using factorized parameters. So it could mimic most other matrix factorization models by feature engineering. Due to the superior flexible, Factorization Machines has already been widely used in many recommended algorithm competitions and practical online recommended system. But, because of the prevalence of large dataset, there is a need to improve the scalability of computation in factorization machines model. In this paper, we propose a parallel algorithm can be used on Factorization Machines model. the experimental results show that the proposed algorithm has good speed-up and scalability on big dataset.

关键词： Frequency modulation Computational modeling Data models Computers parallel algorithms Stochastic processes Algorithm design and analysis

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parallel implementations of LEA 10

Parallel implementations of LEA

引用

10th IFIP WG 11.9 international conference on Digital Forensics

作者： Seo, Hwajeong Liu, Zhe Park, Taehwan Kim, Hyunjin Lee, Yeoncheol Choi, Jongseok Kim, Howon School of Computer Science and Engineering Pusan National University San-30 Jangjeon-Dong Geumjeong-GuBusan609-735 Korea Republic of University of Luxembourg 6 Rue R. Coudenhove-Kalergi 1359 Luxembourg-Kirchberg Luxembourg

ISBN: (纸本)9783319121598

LEA is a new lightweight and low-power encryption algorithm. this algorithm has a certain useful features which are especially suitable for parallel hardware and software implementations, i.e., simple ARX operations, non-S-BOX architecture, and 32-bit word size. In this paper we evaluate the performance of the LEA algorithm on ARMNEON and GPUs by taking advantage of both the desirable features of LEA and a parallel computing platform and programming model by NEON and CUDA. Specifically, we propose novel parallel LEA implementations on representative SIMT and SIMD architectures such as CUDA and NEON. In case of CUDA, we firstly designed a threadbased computation model to fall into functional parallelism by computing several encryptions over one thread. To alleviate the memory transfer delay, we allocate memory to satisfy coalescing memory access. Secondly our method is block cipher implementation written in assembly language, which provides efficient and flexible programming environments. With these optimization techniques, we achieved 17.352 and 2.5GBps (bytes per second) throughput without/with memory transfer. In case of NEON, we adopted pipeline instructions and SIMD-based execution models, which enhanced encryption by 49.85% compared to previous ARM implementations. © Springer international Publishing Switzerland 2014.

关键词： Neon

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parallelizing sparse recovery algorithms: A stochastic approach

Parallelizing sparse recovery algorithms: A stochastic appro...

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international conference on Digital Signal processing (DSP)

作者： Achal Shah Angshul Majumdar Indian Institute of Technology Guwahati Indraprastha Institute of Information Technology Delhi

this work proposes a novel technique for accelerating sparse recovery algorithms on multi-core shared memory architectures. All prior works attempt to speed-up algorithms by leveraging the speed-ups in matrix-vector products offered by the GPU. A major limitation of these studies is that in most signal processing applications, the operators are not available as explicit matrices but as implicit fast operators. In such a practical scenario, the prior techniques fail to speed up the sparse recovery algorithms. Our work is based on the principles of stochastic gradient descent. the main sequential bottleneck of sparse recovery methods is a gradient descent step. Instead of computing the full gradient, we compute multiple stochastic gradients in parallel cores; the full gradient is estimated by averaging these stochastic gradients. the other step of sparse recovery algorithms is a shrinkage operation which is inherently parallel. Our proposed method has been compared with existing sequential algorithms. We find that our method is as accurate as the sequential version but is significantly faster - the larger the size of the problem, the faster is our method.

关键词： Signal processing algorithms Sparse matrices Acceleration Vectors Graphics processing units Digital signal processing

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An improved simulated annealing heuristic for static partitioning of task graphs onto heterogeneous architectures

An improved simulated annealing heuristic for static partiti...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Aravind Vasudevan Avinash Malik David Gregg Trinity College School of Computer Science and Statistics Dublin University of Auckland

We present a simulated annealing based partitioning technique for mapping task graphs, onto heterogeneous processing architectures. Task partitioning onto homogeneous architectures to minimize the makespan of a task graph, is a known NP-hard problem. Heterogeneity greatly complicates the aforementioned partitioning problem, thus making heuristic solutions essential. A number of heuristic approaches have been proposed, some using simulated annealing. We propose a simulated annealing method with a novel NEXT STATE function to enable exploration of different regions of the global search space when the annealing temperature is high and making the search more local as the temperature drops. the novelty of our approach is two fold: (1) we go a step further than the existing scientific literature, considering heterogeneity at levels of task parallelism, data parallelism and communication. (2) We present a novel algorithm that uses simulated annealing to find better partitions in the presence of heterogeneous architectures, data parallel execution units, and significant data communication costs. We conduct a statistical analysis of the performance of the proposed method, which shows that our approach clearly outperforms the existing simulated annealing method.

关键词： Simulated annealing parallel processing Computer architecture Linear programming Temperature distribution Heuristic algorithms Standards

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Fast ICA on Modern GPU architectures

Fast ICA on Modern GPU Architectures

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IEEE international conference on parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Max Plauth Frank Feinbube Peter Tröger Andreas Polze Hasso Plattner Institute University of Potsdam Potsdam Germany

Blind Signal Separation is an algorithmic problem class that deals with the restoration of original signal data from a signal mixture. Implementations, such as Fast ICA, are optimized for parallelization on CPU or first-generation GPU hardware. With the advent of modern, compute centered GPU hardware with powerful features such as dynamic parallelism support, these solutions no longer leverage the available hardware performance in the best-possible way. We present an optimized implementation of the FastICA algorithm, which is specifically tailored for next-generation GPU architectures such as Nvidia Kepler. Our proposal achieves a two digit factor of speedup in the prototype implementation, compared to a multithreaded CPU implementation. Our custom matrix multiplication kernels, tailored specifically for the use case, contribute to the speedup by delivering better performance than the state-of-the-art CUBLAS library.

关键词： Graphics processing units Kernel Hardware Signal processing algorithms Matrix decomposition Covariance matrices Computer architecture

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