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Trends of CPU, GPU and FPGA for high-performance computing

Trends of CPU, GPU and FPGA for high-performance computing

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international conference on Field Programmable Logic and Applications

作者： Mário Véstias Horácio Neto INESC-ID/ISEL/IPL Lisbon Portugal INESC-ID Universidade de Lisboa Portugal

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems.

关键词： Field programmable gate arrays Graphics processing units Performance evaluation Market research Table lookup Monte Carlo methods

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SQL-on-Hadoop: Full circle back to shared-nothing database architectures 40th

SQL-on-Hadoop: Full circle back to shared-nothing database a...

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Proceedings of the 40th international conference on Very Large Data Bases, VLDB 2014

作者： Floratou, Avrilia Minhas, Umar Farooq Özcan, Fatma IBM Almaden Research Center United States

SQL query processing for analytics over Hadoop data has recently gained significant traction. Among many systems providing some SQL support over Hadoop, Hive is the first native Hadoop system that uses an underlying framework such as MapReduce or Tez to process SQL-like statements. Impala, on the other hand, represents the new emerging class of SQL-on-Hadoop systems that exploit a shared-nothing parallel database architecture over Hadoop. Both systems optimize their data ingestion via columnar storage, and promote different file formats: ORC and Parquet. In this paper, we compare the performance of these two systems by conducting a set of cluster experiments using a TPC-H like benchmark and two TPC-DS inspired workloads. We also closely study the I/O efficiency of their columnar formats using a set of micro-benchmarks. Our results show that Impala is 3.3X to 4.4X faster than Hive on MapReduce and 2.1X to 2.8X than Hive on Tez for the overall TPC-H experiments. Impala is also 8.2X to 10X faster than Hive on MapReduce and about 4.3X faster than Hive on Tez for the TPC-DS inspired experiments. through detailed analysis of experimental results, we identify the reasons for this performance gap and examine the strengths and limitations of each system. © 2014 VLDB Endowment.

关键词： MapReduce

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Big Data Analytics on PMU Measurements

Big Data Analytics on PMU Measurements

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the 2014 10th international conference on Natural Computation (ICNC 2014) and the 2014 11th international conference on Fuzzy Systems and Knowledge Discovery (FSKD 2014)(第十届自然计算和第十一届模糊系统与知识发现国际会议)

作者： Mukhtaj Khan Phillip Ashton Gareth Taylor Maozhen Li Junyong Liu School of Engineering and Design Brunel University Uxbridge Middlesex UB8 3PH UK School of Electrical Engineering and Information Systems Sichuan University 610065 China

ISBN: (纸本)9781479951499

Phasor Measurement Units(PMUs)are being rapidly deployed in power grids due to their high sampling *** offer a more current and accurate visibility of the power grids than traditional SCADA ***,the high sampling rates of PMUs bring in two major challenges that need to be addressed to fully benefit from these PMU *** one hand,any transient events captured in the PMU measurements can negatively impact the performance of steady state *** the other hand,processing the high volumes of PMU data in a timely manner poses another challenge in *** paper presents PDFA,a parallel detrended fluctuation analysis approach for fast detection of transient events on massive PMU measurements utilizing a computer *** performance of PDFA is evaluated from the aspects of speedup,scalability and accuracy in comparison with the standalone DFA approach.

关键词： detrended fluctuation analysis (DFA),parallel computing,phasor measurement unit (PMU),event detection,Amdahl’s Law.

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SignalPU: A Programming Model for DSP Applications on parallel and Heterogeneous Clusters

SignalPU: A Programming Model for DSP Applications on Parall...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Farouk Mansouri Sylvain Huet Dominique Houzet GIPSA-lab UMR 5216 CNRS/INPG/UJF/Universite Stendhal GRENOBLE CEDEX France

ISBN: (纸本)9781479961245

the biomedical imagery, the numeric communications, the acoustic signal processing and many others gls[dsp] applications are present more and more in the numeric world. they process growing data volume which is represented with more and more accuracy, and use complex algorithms with time constraints to satisfying. Consequently, a high requirement of computing power characterize them. To satisfy this need, it's inevitable today to use parallel and heterogeneous architectures in order to speedup the processing, where the best examples are today's supercomputers like "Tianhe-2" and "Titan" of Top500 ranking. these architectures with their multi-core nodes supported by many-core accelerators offer a good response to this problem. However, they are still hard to program to make performance because of many reasons: parallelism expression, task synchronization, memory management, hardware specifications handling, load balancing. In the present work, we are characterizing DSP applications and propose a programming model based on their distinctiveness in order to implement them easily and efficiently on heterogeneous clusters.

关键词： Programming Digital signal processing Computer architecture parallel processing Kernel Data models Hardware

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High-speed elliptic curve cryptography on the NVIDIA GT200 graphics processing unit

High-speed elliptic curve cryptography on the NVIDIA GT200 g...

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10th international conference on Information Security Practice and Experience, ISPEC 2014

作者： Cui, Shujie Großschädl, Johann Liu, Zhe Xu, Qiuliang Shandong University School of Computer Science and Technology Shunhua Road 1500 Jinan 250101 Shandong China University of Luxembourg Laboratory of Algorithmics Cryptology and Security 6 rue Richard Coudenhove-Kalergi L-1359 Luxembourg Luxembourg

ISBN: (纸本)9783319063195

this paper describes a high-speed software implementation of Elliptic Curve Cryptography (ECC) for GeForce GTX graphics cards equipped with an NVIDIA GT200 Graphics processing Unit (GPU). In order to maximize throughput, our ECC software allocates just a single thread per scalar multiplication and aims to launch as many threads in parallel as possible. We adopt elliptic curves in Montgomery as well as twisted Edwards form, both defined over a special family of finite fields known as Optimal Prime Fields (OPFs). All field-arithmetic operations use a radix-224 representation for the operands (i.e. 24 operand bits are contained in a 32-bit word) to comply with the native (24 ×24)-bit integer multiply instruction of the GT200 platform. We implemented the OPF arithmetic without conditional statements (e.g. if-then clauses) to prevent thread divergence and unrolled the loops to minimize execution time. the scalar multiplication on the twisted Edwards curve employs a comb approach if the base point is fixed and uses extended projective coordinates so that a point addition requires only seven multiplications in the underlying OPF. Our software currently supports elliptic curves over 160-bit and 224-bit OPFs. After a detailed evaluation of numerous implementation options and configurations, we managed to launch 2880 threads on the 30 multiprocessors of the GT200 when the elliptic curve has Montgomery form and is defined over a 224-bit OPF. the resulting throughput is 115k scalar multiplications per second (for arbitrary base points) and we achieved a minimum latency of 19.2 ms. In a fixed-base setting with 256 precomputed points, the throughput increases to some 345k scalar multiplications and the latency drops to 4.52 ms. © 2014 Springer international Publishing.

关键词： Graphics processing unit

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HIGHLY EFFICIENT GRAPHENE BASED CATALYST FOR OXYGEN REDUCTION REACTION

HIGHLY EFFICIENT GRAPHENE BASED CATALYST FOR OXYGEN REDUCTIO...

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10th IUPAC international conference on Novel Materials and their Synthesis NMS-X(IUPAC第十届新材料及其合成国际会议)

作者： Daping He Peng Wu Xu Chen Hui Wu Shichun Mu State Key Laboratory of Advanced Technology for Materials Synthesis and Processing Wuhan University of TechnologyWuhan 430070P.R.China

Hitherto, the low electrochemical stability of the catalyst is one of the big issues hindering the commercial application of proton exchange membrane fuel cells (PEMFCs) . In this work, more stable support materials based on functionalized graphene nanosheets (GNS), porous GNS, heteroatom doped GNS, and alternative GNS composites including GNS/nano-carbon (or nano-ceramics) sandwiches, nanoceramic wedged GNS, and core-shell graphene and amorphous carbon composites are prepared and applied in catalysts towards oxygen reduction reaction (ORR). based on the idea of bifunction of GNS to Pt catalysts, highly active and stable Pt/reduced graphene oxide (RGO) catalysts are developed by tuning the O/C atom ratio of RGO supports where the optimized O/C atom ratio of 0.14 is determined. Meantime, both perfluorosulfonic acid (PFSA) functionalized GNS and sulfonic acid group-grafted RGO supported Pt catalysts show a higher catalytic activity and a lower loss rate of electrochemical active area (ECA) in comparison with that of the plain Pt/GNS and conventional Pt/C catalysts. In addition, the N-doped RGO supported Pt catalyst (Pt/NRGO) is synthesized using a lyophilisation-assisted N-doping method, revealing a higher catalytic activity and a lower ECA loss of the Pt/NRGO catalyst to compare with that of the Pt/GO and Pt/C catalysts. In addition, to tackle the stacking issues of GNS which leads to the low mass transport property, the porous GNS are synthesized. Besides, we also describe a new strategy to synthesize GNS hybrids including GNS/nano-carbon (nano-creamics) sandwiches and nano-ceramic wedged GNS architectures. these unique architectures with highly dispersed Pt NPs exhibit much high catalytic activities towards ORR and an excellent electrochemical stability. At last, a new graphene @ amorphous carbon core-shell material also shows an excellent electrochemical property. this work was supported financially by the National Natural Science Foundation of China (NSFC) (No. 5

关键词： catalysts graphene oxygen reduction fuel cells

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Novel Multi-Layer Network Decomposition Boosting Acceleration of Multi-core algorithms

Novel Multi-Layer Network Decomposition Boosting Acceleratio...

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IEEE 24th international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Grivas, Athanasios K. Mak, Terrence Yakovlev, Alex Wray, Jonny Newcastle Univ Sch Elect & Elect Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

ISBN: (纸本)9781479904945;9781479904938

Complex networks are a technique for the modeling and analysis of large data sets in many scientific and engineering disciplines. Due to their excessive size conventional algorithms and single core processors struggle with the efficient processing of such networks. Employing multi-core graphic processing units (GPUs) could provide sufficient processing power for the analysis of such networks. However, commonly designed algorithms cannot exploit these massively parallel processing power for the analysis of such networks. In this paper, we present the Multi Layer Network Decomposition (MLND) approach which provides a general approach for parallel network analysis using multi-core processors via efficient partitioning and mapping of networks onto GPU architectures. Evaluation using a 336 core GPU graphic card demonstrated a 16x speed-up in complex network analysis relative to a CPU based approach.

关键词： graphics processing units multiprocessing systems parallel processing

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Comparative Analysis of DSP and Intel Processors by Implementing FFTs using parallel Programming for Underwater Signal processing Applications

Comparative Analysis of DSP and Intel Processors by Implemen...

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10th international Bhurban conference on Applied Science and Technology (IBCAST)

作者： Hamid, Umar Shahzad, Haroon Irfan, Muhammad Ctr Excellence Sci & Appl Technol Islamabad Pakistan

ISBN: (纸本)9781467344265;9781467344258

this paper presents Fast Fourier Transform (FFT) benchmark results to measure and compare the performance of various DSP and Intel processors for underwater signal processing applications. this paper aims to show performance enhancement in Intel processors as compared to DSP processors by using parallel programming for implementing signal processing functions in real time. this paper provides results that show a significant decrease in FFT execution time on an Intel based Multicore processor using parallel programming. therefore comparative analysis among different processor architectures presented in this paper will help the system designers in selecting an optimal processor for underwater signal processing applications.

关键词： signal processing FFT multicore processor

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Design Approaches for Mode Decision in HEVC Encoder Exploiting parallelism at CTB Level 10

Design Approaches for Mode Decision in HEVC Encoder <i>Explo...

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10th international conference on Signal processing and Multimedia Applications (SIGMAP)

作者： Adireddy, Ramakrishna Ugare, Suyash PathPartner Technol Consulting Pvt Ltd New Thippasandra Main Raod Bangalore Karnataka India

ISBN: (纸本)9789897581298

As CPU technology trend is strongly moving towards multi-core architectures, HEVC tried to embrace the parallel processing trend to possible extent. Hence, HEVC exploits some of the parallel processing capabilities like tiles, slices and WPP at frame level (Sullivan et al., 2012). Although slices, tiles and WPP can be used to achieve parallelism, they might end-up degrading either visual quality or compression efficiency. To address this problem, this paper tries to summarize/exploit the possible parallel processing capabilities of HEVC at Coding Tree Block (CTB) level with insignificant compromise in video quality and compression.

关键词： Rate-distortion Cost Coding Tree Block (CTB) parallel processing Mode Decision Video Quality (VQ)

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A Locality-Preserving Write Buffer Design for Page-Mapping Multichannel SSDs

A Locality-Preserving Write Buffer Design for Page-Mapping M...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Sheng Min Huang Li Pin Chang Department of Computer Science National Chiao-Tung University Taiwan

ISBN: (纸本)9781479961245

Advanced SSDs employ a RAM-based write buffer to improve their write performance. the buffer intentionally delays write requests in order to reduce flash write traffic and reorders them to minimize the cost of garbage collection. this work presents a novel buffer algorithm for page-mapping multichannel SSDs. We propose grouping temporally or spatially correlated buffer pages and writing these grouped buffer pages to the same flash block. this strategy dramatically increases the probability of bulk data invalidations in flash blocks. In multichannel architectures, channels are assigned to their own groups of buffer pages for writing, and so channel striping does not divide a group of correlated buffer pages into small pieces. We have conducted simulations and experiments using a SSD simulator and a real SSD platform, respectively. Our results show that our design greatly outperforms existing buffer algorithms.

关键词： Ash Writing Buffer storage Algorithm design and analysis parallel processing Heuristic algorithms Correlation

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