检索结果-内蒙古大学图书馆

HIGHLY EFFICIENT GRAPHENE BASED CATALYST FOR OXYGEN REDUCTION REACTION

HIGHLY EFFICIENT GRAPHENE BASED CATALYST FOR OXYGEN REDUCTIO...

10th IUPAC international conference on Novel Materials and their Synthesis NMS-X(IUPAC第十届新材料及其合成国际会议)

作者： Daping He Peng Wu Xu Chen Hui Wu Shichun Mu State Key Laboratory of Advanced Technology for Materials Synthesis and Processing Wuhan University of TechnologyWuhan 430070P.R.China

Hitherto, the low electrochemical stability of the catalyst is one of the big issues hindering the commercial application of proton exchange membrane fuel cells (PEMFCs) . In this work, more stable support materials based on functionalized graphene nanosheets (GNS), porous GNS, heteroatom doped GNS, and alternative GNS composites including GNS/nano-carbon (or nano-ceramics) sandwiches, nanoceramic wedged GNS, and core-shell graphene and amorphous carbon composites are prepared and applied in catalysts towards oxygen reduction reaction (ORR). based on the idea of bifunction of GNS to Pt catalysts, highly active and stable Pt/reduced graphene oxide (RGO) catalysts are developed by tuning the O/C atom ratio of RGO supports where the optimized O/C atom ratio of 0.14 is determined. Meantime, both perfluorosulfonic acid (PFSA) functionalized GNS and sulfonic acid group-grafted RGO supported Pt catalysts show a higher catalytic activity and a lower loss rate of electrochemical active area (ECA) in comparison with that of the plain Pt/GNS and conventional Pt/C catalysts. In addition, the N-doped RGO supported Pt catalyst (Pt/NRGO) is synthesized using a lyophilisation-assisted N-doping method, revealing a higher catalytic activity and a lower ECA loss of the Pt/NRGO catalyst to compare with that of the Pt/GO and Pt/C catalysts. In addition, to tackle the stacking issues of GNS which leads to the low mass transport property, the porous GNS are synthesized. Besides, we also describe a new strategy to synthesize GNS hybrids including GNS/nano-carbon (nano-creamics) sandwiches and nano-ceramic wedged GNS architectures. these unique architectures with highly dispersed Pt NPs exhibit much high catalytic activities towards ORR and an excellent electrochemical stability. At last, a new graphene @ amorphous carbon core-shell material also shows an excellent electrochemical property. this work was supported financially by the National Natural Science Foundation of China (NSFC) (No. 5

关键词： catalysts graphene oxygen reduction fuel cells

来源：评论

学校读者我要写书评

暂无评论

Novel Multi-Layer Network Decomposition Boosting Acceleration of Multi-core algorithms

Novel Multi-Layer Network Decomposition Boosting Acceleratio...

引用

IEEE 24th international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Grivas, Athanasios K. Mak, Terrence Yakovlev, Alex Wray, Jonny Newcastle Univ Sch Elect & Elect Engn Newcastle Upon Tyne NE1 7RU Tyne & Wear England

ISBN: (纸本)9781479904945;9781479904938

Complex networks are a technique for the modeling and analysis of large data sets in many scientific and engineering disciplines. Due to their excessive size conventional algorithms and single core processors struggle with the efficient processing of such networks. Employing multi-core graphic processing units (GPUs) could provide sufficient processing power for the analysis of such networks. However, commonly designed algorithms cannot exploit these massively parallel processing power for the analysis of such networks. In this paper, we present the Multi Layer Network Decomposition (MLND) approach which provides a general approach for parallel network analysis using multi-core processors via efficient partitioning and mapping of networks onto GPU architectures. Evaluation using a 336 core GPU graphic card demonstrated a 16x speed-up in complex network analysis relative to a CPU based approach.

关键词： graphics processing units multiprocessing systems parallel processing

来源：评论

学校读者我要写书评

暂无评论

Comparative Analysis of DSP and Intel Processors by Implementing FFTs using parallel Programming for Underwater Signal processing Applications

Comparative Analysis of DSP and Intel Processors by Implemen...

引用

10th international Bhurban conference on Applied Science and Technology (IBCAST)

作者： Hamid, Umar Shahzad, Haroon Irfan, Muhammad Ctr Excellence Sci & Appl Technol Islamabad Pakistan

ISBN: (纸本)9781467344265;9781467344258

this paper presents Fast Fourier Transform (FFT) benchmark results to measure and compare the performance of various DSP and Intel processors for underwater signal processing applications. this paper aims to show performance enhancement in Intel processors as compared to DSP processors by using parallel programming for implementing signal processing functions in real time. this paper provides results that show a significant decrease in FFT execution time on an Intel based Multicore processor using parallel programming. therefore comparative analysis among different processor architectures presented in this paper will help the system designers in selecting an optimal processor for underwater signal processing applications.

关键词： signal processing FFT multicore processor

来源：评论

学校读者我要写书评

暂无评论

Design Approaches for Mode Decision in HEVC Encoder Exploiting parallelism at CTB Level 10

Design Approaches for Mode Decision in HEVC Encoder <i>Explo...

引用

10th international conference on Signal processing and Multimedia Applications (SIGMAP)

作者： Adireddy, Ramakrishna Ugare, Suyash PathPartner Technol Consulting Pvt Ltd New Thippasandra Main Raod Bangalore Karnataka India

ISBN: (纸本)9789897581298

As CPU technology trend is strongly moving towards multi-core architectures, HEVC tried to embrace the parallel processing trend to possible extent. Hence, HEVC exploits some of the parallel processing capabilities like tiles, slices and WPP at frame level (Sullivan et al., 2012). Although slices, tiles and WPP can be used to achieve parallelism, they might end-up degrading either visual quality or compression efficiency. To address this problem, this paper tries to summarize/exploit the possible parallel processing capabilities of HEVC at Coding Tree Block (CTB) level with insignificant compromise in video quality and compression.

关键词： Rate-distortion Cost Coding Tree Block (CTB) parallel processing Mode Decision Video Quality (VQ)

来源：评论

学校读者我要写书评

暂无评论

A Locality-Preserving Write Buffer Design for Page-Mapping Multichannel SSDs

A Locality-Preserving Write Buffer Design for Page-Mapping M...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Sheng Min Huang Li Pin Chang Department of Computer Science National Chiao-Tung University Taiwan

ISBN: (纸本)9781479961245

Advanced SSDs employ a RAM-based write buffer to improve their write performance. the buffer intentionally delays write requests in order to reduce flash write traffic and reorders them to minimize the cost of garbage collection. this work presents a novel buffer algorithm for page-mapping multichannel SSDs. We propose grouping temporally or spatially correlated buffer pages and writing these grouped buffer pages to the same flash block. this strategy dramatically increases the probability of bulk data invalidations in flash blocks. In multichannel architectures, channels are assigned to their own groups of buffer pages for writing, and so channel striping does not divide a group of correlated buffer pages into small pieces. We have conducted simulations and experiments using a SSD simulator and a real SSD platform, respectively. Our results show that our design greatly outperforms existing buffer algorithms.

关键词： Ash Writing Buffer storage Algorithm design and analysis parallel processing Heuristic algorithms Correlation

来源：评论

学校读者我要写书评

暂无评论

T3B: Recent advancements in fiber optic transmission enabled by highly integrated mixed signal SoC and advanced digital signal processing

T3B: Recent advancements in fiber optic transmission enabled...

引用

IEEE international SOC conference

作者： Han Sun Infinera

Mixed signal SoC has always played an important role in long haul, high capacity fiber optic transmission systems. In early days of 10Gbit NRZ transmission, the functions were simple, but implementing decision device, clock recovery and de-multiplexing functions at such high data rate was challenging at the time. In the span of 15 years, the single channel data rate and network capacities have increased 20x, owing to a fundamental change in the way data is modulated and demodulated over the fiber optic channel. Intensity modulation and direct detection has given way to coherent detection and advanced modulation formats such as Polarization-Multiplexed QPSK and higher order QAM. Today, commercial state-of-art single channel data rate have reached 100Gbit/s. 400Gbit/s data rates are being attempted in the laboratory. these astounding achievements are not possible without the parallel advancements in CMOS technology. High speed A/D and D/A converters implemented in CMOS side-by-side with massively parallel, highly dense digital circuits is a key enabler in delivering the network capacities demanded by network operators and consumers. In this tutorial, we first review the challenges of the fiber optic channel, and introduce the necessary digital signal processing functions that need to be implemented in the SOC. We provide some example implementations of clock recovery, carrier recovery and equalization algorithms. We will also review forward error correction methods adopted in the most state-of-art designs. We conclude by discussing the challenges in designing next generation transceiver ASICs.

关键词： Optical fibers Clocks Coherence Digital signal processing Intensity modulation Optical signal processing

来源：评论

学校读者我要写书评

暂无评论

parallel Numerical Optimization for Fast Adaptive Nonlinear Moving Horizon Estimation

Parallel Numerical Optimization for Fast Adaptive Nonlinear ...

引用

10th IEEE international conference on Networking, Sensing and Control (ICNSC)

作者： Poloni, Tomas Rohal'-Ilkiv, Boris Johansen, Tor Arne Slovak Univ Technol Bratislava Fac Mech Engn Inst Automat Measurement & Appl Informat Bratislava Slovakia Norwegian Univ Sci & Technol Dept Engn Cybernet Trondheim Norway

ISBN: (纸本)9781467352000;9781467351980

this paper proposes a novel strategy using parallel optimization computations for nonlinear moving horizon state estimation, and parameter identification problems of dynamic systems. the parallelization is based on the multi-point derivative-based Gauss-Newton search, as one of the most efficient algorithms for the nonlinear least-square problems. A numerical experiment is performed to demonstrate the parallel computations with the comparison to sequential computations.

关键词： Moving horizon state estimation Parameter identification parallel Lines sequential computation nonlinearity parallel processing (COMPUTERS) Horizon State estimation Numerical

来源：评论

学校读者我要写书评

暂无评论

Fast and accurate implementation of Canny edge detector on embedded many-core platform

Fast and accurate implementation of Canny edge detector on e...

引用

Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Taieb Lamine Ben Cheikh Gabriela Nicolescu Jelena Trajkovic Youcef Bouchebaba Pierre Paulin Department of Computer Engineering Ecole Polytechnique de Montréal Montréal Canada Department of Electrical and Computer Engineering Concordia University Montréal Canada Synopsys Inc. Ottawa Canada

Image processing and computer vision applications are used intensively in several domains in particular multimedia and medicine. the main challenge in developing such applications is how to guarantee both high accuracy and low execution time. Accordingly, we observe two research directions: the first focuses on improving the algorithms and the second focuses on designing fast hardware platforms. In this paper, we propose an efficient parallel implementation of an accurate extended Canny edge detection algorithm suitable for medical applications on embedded many-core platform. the proposed implementation is running at a frame rate of 10 frames/s for image size of 512×512 with high accurate and smooth line edges.

关键词： Image edge detection Computer architecture Fabrics Accuracy Graphics processing units Hardware Real-time systems

来源：评论

学校读者我要写书评

暂无评论

Neuromorphic processing: a new frontier in scaling computer architecture 14

Neuromorphic processing: a new frontier in scaling computer ...

引用

Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

作者： Jeff Gehlhaar Qualcomm Technologies Inc. San Diego CA USA

ISBN: (纸本)9781450323055

the desire to build a computer that operates in the same manner as our brains is as old as the computer itself. Although computer engineering has made great strides in hardware performance as a result of Dennard scaling, and even great advances in 'brain like' computation, the field still struggles to move beyond sequential, analytical computing architectures. Neuromorphic systems are being developed to transcend the barriers imposed by silicon power consumption, develop new algorithms that help machines achieve cognitive behaviors, and both exploit and enable further research in neuroscience. In this talk I will discuss a system im-plementing spiking neural networks. these systems hold the promise of an architecture that is event based, broad and shallow, and thus more power efficient than conventional computing solu-tions. this new approach to computation based on modeling the brain and its simple but highly connected units presents a host of new challenges. Hardware faces tradeoffs such as density or lower power at the cost of high interconnection overhead. Consequently, software systems must face choices about new language design. Highly distributed hardware systems require complex place and route algorithms to distribute the execution of the neural network across a large number of highly interconnected processing units. Finally, the overall design, simulation and testing process has to be entirely reimagined. We discuss these issues in the context of the Zeroth processor and how this approach compares to other neuromorphic systems that are becoming available.

关键词： spiking neural network parallel computing low power zeroth neural network neuromorphic

来源：评论

学校读者我要写书评

暂无评论

Test Harness on a Preconditioned Conjugate Gradient Solver on GPUs: An Efficiency Analysis

引用

IEEE TRANSACTIONS ON MAGNETICS 2013年第5期49卷 1729-1732页

作者： Rodrigues, A. Wendell de O. Chevallier, Loic Le Menach, Yvonnick Guyomarch, Frederic Univ Lille 1 LIFL F-59655 Villeneuve Dascq France Univ Lille 1 L2EP F-59655 Villeneuve Dascq France

the parallelization of numerical simulation algorithms, i.e., their adaptation to parallel processing architectures, is an aim to reach in order to hinder exorbitant execution times. the parallelism has been imposed at the level of processor architectures and graphics cards are now used for general-purpose calculation, also known as "General-Purpose computation on Graphics processing Unit (GPGPU)". the clear benefit is the excellent performance over price ratio. Besides hiding the low level programming, software engineering leads to a faster and more secure application development. this paper presents the real interest of using GPU processors to increase performance of larger problems which concern electrical machines simulation. Indeed, we show that our auto-generated code applied to several models allows achieving speedups of the order of 10 x.

关键词： Gradient methods numerical simulation parallel architectures software engineering

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：