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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2811 条记录，以下是1281-1290 订阅

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Ray-Tracing-Based Geospatial Optimization for Heterogeneous architectures Enhancing Situational Awareness

Ray-Tracing-Based Geospatial Optimization for Heterogeneous ...

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IEEE 16th international conference on Computational Science and Engineering (CSE)

作者： Richie, David A. Ross, James A. Park, Song J. Shires, Dale R. Brown Deer Technol Forest Hill MD 21050 USA Dynam Res Corp Andover MA 01810 USA US Army Res Lab Aberdeen Proving Ground MD 21005 USA

ISBN: (纸本)9781479948970

this paper presents the implementation of ray-tracing-based algorithms for multi-objective geospatial optimization targeting various many-core processing technologies such as graphics processing units, x86 multi-cores, and ARM processors. High performance is achieved through highly parallel core algorithms, executed on multiple compute devices across a heterogeneous architecture using low-level OpenCL kernels. algorithms for calculating line-of-sight ballistic threat, visual observability, ground plane extraction, and Markov chain Monte Carlo optimization provide an augmented geospatial intelligence and situational awareness in three-dimensional urban environments.

关键词： GPGPU parallel computing heterogeneous systems line-of-sight geospatial optimization

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algorithms and architectures for parallel processing - 12th international conference, ICA3PP 2012, Proceedings

Algorithms and Architectures for Parallel Processing - 12th ...

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12th international conference on algorithms and architectures for parallel processing, ICA3PP 2012

ISBN: (纸本)9783642330773

the proceedings contain 73 papers. the topics discussed include: accelerating the dynamic programming for the optimal polygon triangulation on the GPU;security computing for the resiliency of protecting from internal attacks in distributed wireless sensor networks;optimization of a short-range proximity effect correction algorithm in e-beam lithography using GPGPUs;vectorized algorithms for Quadtree construction and descent;an optimal parallel prefix-sums algorithm on the memory machine models for GPUs;enhancing the performance of a distributed mobile computing environment by topology construction;maintaining consistency in software transactional memory through dynamic versioning tuning;a new low latency parallel turbo decoder employing parallel phase decoding method;high-performance matrix multiply on a massively multithreaded Fiteng1000 processor;and on construction of Cloud IaaS for VM live migration using KVM and OpenNebula.

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Conflict-free data access for multi-bank memory architectures using padding

Conflict-free data access for multi-bank memory architecture...

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20th international conference on High Performance Computing (HiPC)

作者： Sohl, Joar Wang, Jian Karlsson, Andreas Liu, Dake Linkoping Univ Dept Comp Engn Linkoping Sweden

ISBN: (纸本)9781479907298

For high performance computation memory access is a major issue. Whether it is a supercomputer, a GPGPU device, or an Application Specific Instruction set Processor (ASIP) for Digital Signal processing (DSP) parallel execution is a necessity. A high rate of computation puts pressure on the memory access, and it is often non-trivial to maximize the data rate to the execution units. Many algorithms that from a computational point of view can be implemented efficiently on parallel architectures fail to achieve significant speed-ups. the reason is very often that the speed-up possible with the available execution units are poorly utilized due to inefficient data access. this paper shows a method for improving the access time for sequences of data that are completely static at the cost of extra memory. this is done by resolving memory conflicts by using padding. the method can be automatically applied and it is shown to significantly reduce the data access time for sorting and FFTs. the execution time for the FFT is improved with up to a factor of 3.4 and for sorting by a factor of up to 8.

关键词： Access to Information information retrieval PADDING Memory architecture sorting programs parallel architectures Storage access times execution time Data transfer rates Memory Memory Fast Fourier transform Digital signal processing

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On the Impact of Fractal Organization on the Performance of Socio-technical Systems

On the Impact of Fractal Organization on the Performance of ...

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IEEE 10th international conference on Ubiquitous Intelligence and Computing (UIC) / IEEE 10th international conference on Autonomic and Trusted Computing (ATC)

作者： De Florio, Vincenzo Sun, Hong Buys, Jonas Blondia, Chris Univ Antwerp iMinds Res Inst PATS Res Grp Middelheimlaan 1 B-2020 Antwerp Belgium AGFA Hlth Care Ghent Belgium

ISBN: (纸本)9781479924813

Fractal organizations are a class of bio-inspired distributed hierarchical architectures in which control and feedback information are allowed to flow independently of the position the participating nodes have in the system hierarchy. In this paper we discuss the adoption of a fractal organization in a class of socio-technical systems characterized by a centralized architecture. We present the key architectural traits of the resulting Fractal Social Organization and put forward our conjecture that services based on the presented solution may exhibit significant improvements, e.g., in terms of scalability and performance. In order to provide elements to justify our conjecture we describe how we envision the use of the new organization in two different cases: a framework for semantic service description-and-matching and a low-cost telemonitoring service.

关键词： Distributed organizations Fractal organization Fractal social organizations Middleware technology Semantic processing Social Overlay Networks

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Scalability and Efficiency of Database Queries on Future Many-core Systems

Scalability and Efficiency of Database Queries on Future Man...

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21st Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Petrides, Panayiotis Diavastos, Andreas Christofi, Constantinos Trancoso, Pedro Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9780769549392;9781467353212

Decision Support System (DSS) workloads are known to be one of the most time-consuming database workloads that process large data sets. Traditionally, DSS queries have been accelerated using large-scale multiprocessors. In this work we exploit the benefits of using future many-core architectures, more specifically on-chip clustered many-core architectures. To achieve this goal we propose different representative data parallel versions of the original database scan and join algorithms. We also study the impact on the performance when on-chip memory, shared among all cores, is used as a prefetching buffer. For our experiments we study the behaviour of three queries from the standard DSS benchmark TPC-H executing on the Intel Single chip Cloud Computer experimental processor (Intel SCC). Our results show that parallelism can be well exploited by such architectures and how important it is to have a balance between computation and data intensity. Moreover, from our experimental results we show that performance improvement of 5x and 10x for the corresponding query implementation without data prefetching. Finally we show how we could efficiently use the system in order to achieve high power-performance efficiency when using the proposed prefetching buffer.

关键词： buffer storage coprocessors decision support systems parallel architectures query processing shared memory systems

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QbDJ: A Novel Framework for Handling Skew in parallel Join processing on Distributed Memory

QbDJ: A Novel Framework for Handling Skew in Parallel Join P...

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15th IEEE international conference on High Performance Computing and Communications (HPCC) /11th IEEE/IFIP international conference on Embedded and Ubiquitous Computing (EUC)

作者： Cheng, Long Kotoulas, Spyros Ward, Tomas E. theodoropoulos, Georgios Natl Univ Ireland Maynooth Kildare Ireland IBM Res Dublin Ireland Univ Durham Durham DH1 3HP England

ISBN: (纸本)9780769550886

the performance of parallel distributed data management systems becomes increasingly important with the rise of Big Data. parallel joins have been widely studied both in the parallel processing and the database communities. Nevertheless, most of the algorithms so far developed do not consider the data skew, which naturally exists in various applications. State of the art methods designed to handle this problem are based on extensions to either of the two prevalent conventional approaches to parallel joins - the hash-based and duplication-based frameworks. In this paper, we introduce a novel parallel join framework, query-based distributed join (QbDJ), for handling data skew on distributed architectures. Further, we present an efficient implementation of the method based on the asynchronous partitioned global address space (APGAS) parallel programming model. We evaluate the performance of our approach on a cluster of 192 cores (16 nodes) and datasets of 1 billion tuples with different skews. the results show that the method is scalable, and also runs faster with less network communication compared to state-of-art PRPD approach in [1] under high data skew.

关键词： Distributed join parallel join data skew high performance X10

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SPC: An approach to guarantee performance in cost oriented mapping algorithm for NoC architectures

SPC: An approach to guarantee performance in cost oriented m...

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2013 IEEE 8th international conference on Networking, Architecture and Storage, NAS 2013

作者： Wu, Qinghua Liu, Leibo Yin, Shouyi Ren, Yu Wei, Shaojun Institute of Micro-Electronics and National Laboratory for Information Science and Technology Tsinghua University Beijing 100084 China

ISBN: (纸本)9780769550343

How to map IP cores onto NoC architectures is a significant issue (application mapping) in multi-core system design. Many mapping algorithms which aim at optimizing cost metrics(e.g. energy consumption) in the mapping procedure are proposed. Some of those algorithms consider satisfying performance metrics (e.g. latency) constraints. this paper analyses the mechanism leading to performance decreases and furthermore proposes a new approach SPC (satisfy processing capacity) to guarantee performance metrics for cost oriented application mapping algorithms. Using this approach in one of those algorithms, performance metrics constraints are well ensured and cost metrics are hardly affected. In fact, one random experiment shows that performance is enhanced at most 10% even if cost is reduced by 6%. © 2013 IEEE.

关键词： Network-on-chip

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parallelization of Discrete Stochastic Arithmetic on multicore architectures

Parallelization of Discrete Stochastic Arithmetic on multico...

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10th international conference on Information Technology - New Generations (ITNG)

作者： Jezequel, F. Lamotte, J-L Chubach, O. Univ Paris 06 UMR 7606 Lab Informat Paris 6 4 Pl Jussieu F-75252 Paris 05 France Odessa I I Mechnikov Natl Univ UA-65082 Odessa Ukraine

ISBN: (纸本)9780769549675

Discrete Stochastic Arithmetic (DSA) estimates round-off error propagation in a program. It is based on a synchronous execution of several instances of the program to control using a random rounding mode. In this paper we show how we can take advantage of multicore processors, which are nowadays widespread, to reduce the cost of DSA in terms of execution time. Several processes execute in parallel different instances of the program and exchange data when necessary. Several strategies are compared for the estimation of the result accuracy and the detection of numerical instabilities. With our parallel implementation, the cost of DSA is reduced by a factor of about 2 compared with the sequential approach. Our parallel implementation of DSA has been used successfully for the numerical validation of a real-life application.

关键词： Discrete Stochastic Arithmetic floating-point arithmetic multicore processors numerical validation round-off errors

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parallel Implementation of Real-Time Semi-Global Matching on Embedded Multi-Core architectures

Parallel Implementation of Real-Time Semi-Global Matching on...

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13th international conference on Embedded Computer Systems - architectures, Modeling and Simulation (IC-SAMOS)

作者： Arndt, Oliver Jakob Becker, Daniel Banz, Christian Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Corporate Techn D-81739 Munich Germany

ISBN: (纸本)9781479901036

Embedded real-time algorithms are often realized with dedicated hardware, exhibiting high production costs and low programming flexibility thereafter. For instance, semi-global matching for stereo image processing, including complex data flows, traditionally runs on customized hardware modules. Combining the processing and memory capabilities of multiple individual cores, emerging embedded multi-core technologies address these problems. However, considering concurrency issues (e. g., data races and lock contentions), parallel programming requires experienced programmers and technology-specific techniques (e. g., synchronization libraries) and tools (e. g., parallel profilers), which are often not available on embedded platforms. In this work, we introduce a parallel version of a semi-global matching algorithm and demonstrate within this case study runtime optimizations necessary to meet real-time requirements. We also show structured steps of the applied parallelization workflow, illustrating an efficient migration strategy to multi-core platforms using runtime information (e. g., profiles and hardware counters). Finally, to evaluate the resulting performance characteristics, we compare the runtime behavior of the parallel version running on a Freescale P4080 processor with reference values taken on an Intel i7, a field-programmable logic device, an extended general purpose processor and a GPU.

关键词： concurrency control embedded systems image matching multiprocessing systems parallel architectures parallel programming performance evaluation

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A Hybrid parallel Barnes-Hut Algorithm for GPU and Multicore architectures

A Hybrid Parallel Barnes-Hut Algorithm for GPU and Multicore...

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19th international conference on Euro-Par

作者： Hannak, Hannes Hochstetter, Hendrik Blochinger, Wolfgang Univ Stuttgart Inst Parallel & Distributed Syst Stuttgart Germany Univ Siegen Comp Graph & Multimedia Syst Grp D-57068 Siegen Germany

ISBN: (纸本)9783642400476

Using the Barnes-Hut algorithm as an example we deal with the design of parallel algorithms that are able to exploit multicore CPUs and GPUs conjointly. Specifically, we demonstrate how to modularize a parallel application according to specific aspects of parallel execution. this allows for a flexible assignment of individual modules to the two parallel architectures based on their actual performance characteristics. Furthermore, we discuss a hybrid module for the most time consuming part of the algorithm that utilizes CPU and GPU simultaneously employing a novel load balancing heuristic. Our experimental evaluation shows that our method greatly increases overall efficiency by allowing to deploy the optimal configuration of modules for each individual computer system.

关键词： Graphics processing unit

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