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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Memory efficient Multi-Swarm PSO algorithm in OpenCL on an APU

Memory efficient Multi-Swarm PSO algorithm in OpenCL on an A...

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13th international conference on algorithms and architectures for parallel processing, ICA3PP 2013

作者： Franz, Wayne thulasiraman, Parimala thulasiram, Ruppa K. University of Manitoba Canada

ISBN: (纸本)9783319038582

Multi-Swarm PSO (MPSO) is an extension of the PSO algorithm that incorporates multiple, collaborating swarms. Although embarrassingly parallel in appearance, MPSO is memory bound, introducing challenges for GPU-based architectures. In this paper, we use device-utilization metrics to drive the development and optimization of an MPSO algorithm applied to the task matching problem. Our hardware architecture is the AMD Accelerated processing Unit (APU), which fuses the CPU and GPU together on a single chip. We make effective use of features such as the hierarchical memory structure on the APU, the 4-way very long instruction word (VLIW) feature for vectorization, and DMA transfer features for asynchronous transfer of data between global memory and local memory. the resulting algorithm provides a 29% decrease in overall execution time over our baseline implementation. © Springer international Publishing Switzerland 2013.

关键词： Graphics processing unit

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parallelizing General Histogram Application for CUDA architectures

Parallelizing General Histogram Application for CUDA Archite...

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13th international conference on Embedded Computer Systems - architectures, Modeling and Simulation (IC-SAMOS)

作者： Milic, Ugljesa Gelado, Isaac Puzovic, Nikola Ramirez, Alex Tomasevic, Milo Ctr Nacl Supercomputac Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna E-08028 Barcelona Spain Univ Belgrade Sch Elect Engn YU-11001 Belgrade Serbia

ISBN: (纸本)9781479901036

Histogramming is a tool commonly used in data analysis. Although its serial version is simple to implement, providing an efficient and scalable way to parallelize it can be challenging. this especially holds in case of platforms that contain one or several massively parallel devices like CUDA-capable GPUs due to issues with domain decomposition, use of global memory and similar. In this paper we compare two approaches for implementing general purpose histogramming on GPUs. the first algorithm is based on private copies of bin counters stored in shared memory for each block of threads. the second one uses the thrust library to sort the input elements and then to search for upper bounds according to bin widths. For both algorithms we analyze how the speedup over the sequential version depends on the size of input collection, number of bins, and the type and distribution of input elements. We also implement overlapping of data transfers between host CPU and CUDA device with kernel execution. For both algorithms we analyze the pros and cons in detail. For example, privatization strategy can be up to 2x faster than sort-search with realistic inputs, but can only support a limited number of bins. On the other hand, sort-search strategy has about 50% higher speedup than privatization when we use characters as input and can support unlimited number of bins. Finally, we perform an exploration to determine the optimal algorithm depending on the characteristics and values of input parameters.

关键词： data analysis graphics processing units parallel architectures shared memory systems

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A high performance VLSI architecture for integer motion estimation in HEVC

A high performance VLSI architecture for integer motion esti...

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2013 IEEE 10th international conference on ASIC, ASICON 2013

作者： Yuan, Xu Liu, Jinsong Gong, Liwei Zhi, Zhang Teng, Robert K.F. Shenzhen Key Lab of Advanced Communication and Information Processing College of Information Engineering Shenzhen University Shenzhen 518000 China Department of Electrical Engineering California State University Long Beach 90840 United States

ISBN: (纸本)9781467364157

A high performance VLSI architecture for integer motion estimation (IME) in High Efficiency Video Coding (HEVC) is presented in this paper. It supports coding tree block (CTB) structure with the asymmetric motion partition (AMP) mode. the architecture contains two parallel sub-architectures to meet 1080p@30fps real-time video coding. the size L×L of CTB in the architecture is set to L=32 pixels by default, and it can be extended to L=64 and L=16 pixels. A serial mode decision module to find optimal partition mode for the architecture has also been implemented. © 2013 IEEE.

关键词： Pixels

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Vectorized Higher Order Finite Difference Kernels

Vectorized Higher Order Finite Difference Kernels

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11th international conference on Applied parallel and Scientific Computing (PARA)

作者： Zumbusch, Gerhard Univ Jena Inst Angew Math D-07743 Jena Germany

ISBN: (纸本)9783642368035

Several highly optimized implementations of Finite Difference schemes are discussed. the combination of vectorization and an interleaved data layout, spatial and temporal loop tiling algorithms, loop unrolling, and parameter tuning lead to efficient computational kernels in one to three spatial dimensions, truncation errors of order two to twelve, and isotropic and compact anisotropic stencils. the kernels are implemented on and tuned for several processor architectures like recent Intel Sandy Bridge, Ivy Bridge and AMD Bulldozer CPU cores, all with AVX vector instructions as well as Nvidia Kepler and Fermi and AMD Southern and Northern Islands GPU architectures, as well as some older architectures for comparison. the kernels are either based on a cache aware spatial loop or on time-slicing to compute several time steps at once. Furthermore, vector components can either be independent, grouped in short vectors of SSE, AVX or GPU warp size or in larger virtual vectors with explicit synchronization. the optimal choice of the algorithm and its parameters depend both on the Finite Difference stencil and on the processor architecture.

关键词： Graphics processing unit

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Collision energy mitigation through active control of future lightweight vehicle architectures

Collision energy mitigation through active control of future...

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10th international conference on Informatics in Control, Automation and Robotics, ICINCO 2013

作者： Trollope, James E. Burnham, Keith J. Control Theory and Applications Centre Faculty of Engineering and Computing Coventry University Coventry CV1 5FB United Kingdom

ISBN: (纸本)9789898565716

the paper challenges the current state-of-the-art which is accepted by the automotive industry. Present day vehicles are unsophisticatedly over-engineered and, as a consequence, are uneconomic, hence unsustainable. Vehicles currently under development, however, offer tremendous opportunities for shifting from this position to include onboard active safety systems, e.g. collision avoidance. It is argued that future vehicles should be significantly lighter and exploit the developing safety features to the full. Indeed, such a development would reduce the existing need for crashworthiness. the above arguments coupled with parallel developments in smart materials, paves the way towards a new generation of actively controlled vehicle architecture design. Whilst the move to lighter vehicles, with onboard active safety systems and actively controlled structures, may be seen as controversial, there is a convincing case for a paradigm shift towards a truly sustainable transport future.

关键词： Vehicle safety

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Convergence throughput Gain in a Unified parallel Turbo Receiver

Convergence Throughput Gain in a Unified Parallel Turbo Rece...

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10th international Bhurban conference on Applied Science and Technology (IBCAST)

作者： Jafri, Atif Raza Baghdadi, Amer CESAT Islamabad Pakistan

ISBN: (纸本)9781467344265;9781467344258

In pursuit of bringing high end applications on radio platforms, recent and evolving wireless standards impose stringent requirements in the shape of high throughputs, error rate performance close to theoretical limits and multi mode transmissions to efficiently use bandwidth in different channel conditions. In the presence of these requirements, the designer comes across contradicting requirements. In fact, in order to handle error rate performance the iterative (Turbo) processing (Turbo/LDPC decoding, Turbo demodulation and Turbo Equalization) is common implementation practice in baseband receivers. However, this creates bottleneck in achieving imposed throughputs. In this scenario, parallelism study and resulting throughput gains while keeping same error rate convergence, provides the designer concrete results to establish compromise among design constraints. In this paper, first of all three level of parallelism study is presented on turbo decoding, turbo demodulation and MIMO turbo equalization. To aid the designer in taking decision during the design, mathematical expressions for throughput gain in unified parallel turbo receiver are provided. throughput gain for different system scenarios are computed by using system parameters and simulation results in derived expressions.

关键词： Wireless communications MIMO parallelism high throughput

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General-Purpose Graphics processing Units in Service-Oriented architectures

General-Purpose Graphics Processing Units in Service-Oriente...

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6th IEEE international conference on Service-Oriented Computing and Applications (SOCA)

作者： Calatrava Moreno, Maria del Carmen Auzinger, thomas Vienna Univ Technol E Commerce Grp A-1040 Vienna Austria Vienna Univ Technol Inst Comp Graph & Algorithms A-1040 Vienna Austria

ISBN: (纸本)9781479927012

Over the last decades, graphics processing units have developed from special-purpose graphics accelerators to general-purpose massively parallel co-processors. In recent years they gained increased traction in high performance computing, as they provide superior computational performance in terms of runtime and energy consumption for a wide range of problems. In this survey, we review their employment in distributed computing for a broad range of application scenarios. Common characteristics and a classification of the most relevant use cases are described. Furthermore, we discuss possible future developments of the use of general purpose graphics processing units in the area of service-oriented architecture. the aim of this work is to inspire future research in this field and to give guidelines on when and how to incorporate this new hardware technology.

关键词： Graphics processing unit

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Network and parallel Computing - 10th IFIP international conference, NPC 2013, Proceedings

Network and Parallel Computing - 10th IFIP International Con...

引用

10th IFIP international conference on Network and parallel Computing, NPC 2013

ISBN: (纸本)9783642408199

the proceedings contain 34 papers. the topics discussed include: a virtual network embedding algorithm based on graph theory;access annotation for safe program parallelization;extracting threaded traces in simulation environments;a network-aware virtual machine allocation in cloud datacenter;totoro: a scalable and fault-tolerant data center network by using backup port;a cloud resource allocation mechanism based on mean-variance optimization and double multi-attribution auction;a scheduling method for multiple virtual machines migration in cloud;speeding up Galois field arithmetic on Intel MIC architecture;software/hardware hybrid network-on-chip simulation on FPGA;total exchange routing on hierarchical dual-nets;efficiency of flexible rerouting scheme for maximizing logical arrays;conditional diagnosability of complete Josephus cubes;accelerating parallel frequent itemset mining on graphics processors with sorting;and asymmetry- aware scheduling in heterogeneous multi-core architectures.

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On-Board Multi-GPU Molecular Dynamics

On-Board Multi-GPU Molecular Dynamics

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19th international conference on Euro-Par

作者： Novalbos, Marcos Gonzalez, Jaime Otaduy, Miguel Angel Lopez-Medrano, Alvaro Sanchez, Alberto URJC Madrid Madrid Spain Plebiot SL Madrid Spain

ISBN: (纸本)9783642400476

Molecular dynamics simulations allow us to study the behavior of complex biomolecular systems. these simulations suffer a large computational complexity that leads to simulation times of several weeks in order to recreate just a few microseconds of a molecule's motion even on high-performance computing platforms. In recent years, state-of-the-art molecular dynamics algorithms have benefited from the parallel computing capabilities of multicore systems, as well as GPUs used as co-processors. In this paper we present a parallel molecular dynamics algorithm for on-board multi-GPU architectures. We parallelize a state-of-the-art molecular dynamics algorithm at two levels. We employ a spatial partitioning approach to simulate the dynamics of one portion of a molecular system on each GPU, and we take advantage of direct communication between GPUs to transfer data among portions. We also parallelize the simulation algorithm to exploit the multi-processor computing model of GPUs. Most importantly, we present novel parallel algorithms to update the spatial partitioning and set up transfer data packages on each GPU. We demonstrate the feasibility and scalability of our proposal through a comparative study with NAMD, a well known parallel molecular dynamics implementation.

关键词： Graphics processing unit

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Two Exact Methods For Mapping On Heterogeneous CPU/FPGA architectures

Two Exact Methods For Mapping On Heterogeneous CPU/FPGA Arch...

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10th IEEE international conference on Networking, Sensing and Control (ICNSC)

作者： Souissi, Omar Abdelhakim, Artiba Univ Valenciennes & Hainaut Cambresis LAMIH UMR 8201 F-59313 Le Mt Houy 9 Valenciennes France

ISBN: (纸本)9781467352000;9781467351980

this research investigates the problem of the optimisation of static task mapping on a heterogeneous computing system CPU/FPGA (Central processing Unit/Field-Programmable Gate Array) used to implement intimately coupled hardware and software models. In the face of obstacles as memory-wall, power wall and real-time requirements, hardware designers are directed more and more towards reconfigurable computing. the use of heterogeneous CPU/FPGA systems is one of the most promising solutions in order to increase the performance. Indeed, in such systems, multi-core processors (CPU) provide high computation rates while the reconfigurable logic (FPGA) offers high performance and adaptability to the application real-time constraints. However, heterogeneous computing systems present new challenges, and one of the most important issues is how to map efficiently the application tasks on the available resources while considering real-time constraints. this work includes the development of two exact methods that focus on the static initial task mapping, for two different case studies. In the first case, the execution is considered preemptive and the problem of task mapping is treated in terms of workload on the heterogeneous system. While in the second case the execution is considered non preemptive and the main objective is to minimize the makespan. In both case studies we consider communication constraints, since the application tasks are linked by precedence.

关键词： MAPPING(MAthEMATICAL) mapping application task Heterogeneous Preemptive Time constraints central processing units

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