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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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GCMR: A GPU Cluster-Based MapReduce Framework for Large-Scale Data processing

GCMR: A GPU Cluster-Based MapReduce Framework for Large-Scal...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Yiru Guo Weiguo Liu Bin Gong Gerrit Voss Wolfgang Muller-Wittig Sch. of Comput. Sci. & Technol. Shandong Univ. Jinan China Fraunhofer IDM@NTU Nanyang Technol. Univ. Singapore Singapore

MapReduce is a very popular programming model to support parallel and distributed large-scale data processing. there have been a lot of efforts to implement this model on commodity GPU-based systems. However, most of these implementations can only work on a single GPU. And they can not be used to process large-scale datasets. In this paper, we present a new approach to design the MapReduce framework on GPU clusters for handling large-scale data processing. We have used Compute Unified Device architectures (CUDA) and MPI parallel programming models to implement this framework. To derive an efficient mapping onto GPU clusters, we introduce a two-level parallelization approach: the inter node level and intra node level parallelization. Furthermore in order to improve the overall MapReduce efficiency, a multi-threading scheme is used to overlap the communication and computation on a multi-GPU node. Compared to previous GPU-based MapReduce implementations, our implementation, called GCMR, achieves speedups up to 2.6 on a single node and up to 9.1 on 4 nodes of a Tesla S1060 quad-GPU cluster system for processing small datasets. It also shows very good scalability for processing large-scale datasets on the cluster system.

关键词： Graphics processing units Instruction sets Computational modeling Computer architecture Acceleration Writing Data processing

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Direction-Optimizing Breadth-First Search on CPU-GPU Heterogeneous Platforms

Direction-Optimizing Breadth-First Search on CPU-GPU Heterog...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Dan Zou Yong Dou Qiang Wang Jinbo Xu Baofeng Li National University of Defense Technology Changsha Hunan CN

Breadth-First Search (BFS) is a basis for many graph traversal and analysis algorithms. In this paper, we present a direction-optimizing BFS implementation on CPU-GPU heterogeneous platforms to fully exploit the computing power of both the multi-core CPU and GPU. For each level of the BFS algorithm, we dynamically choose the best implementation from: a sequential top-down execution on CPU, a parallel top-down execution on CPU, and a cooperative bottom-up execution on CPU and GPU. By adapting to the runtime variability of vertex frontiers, such a hybrid approach provides the best performance for the exploration of each BFS level while avoiding poor worst case performance. Our implementation demonstrates speedups of 1.37 to 1.44 compared to the highest published performance for shared memory systems.

关键词： Graphics processing units Instruction sets Algorithm design and analysis Arrays Kernel Heuristic algorithms

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A high performance VLSI architecture for integer motion estimation in HEVC

A high performance VLSI architecture for integer motion esti...

引用

international conference on ASIC

作者： Xu Yuan Liu Jinsong Gong Liwei Zhang Zhi Robert K. F. Teng Shenzhen Key Lab of Advanced Communication and Information Processing Shenzhen University Shenzhen China Department of Electrical Engineering California State University Long Beach USA

A high performance VLSI architecture for integer motion estimation (IME) in High Efficiency Video Coding (HEVC) is presented in this paper. It supports coding tree block (CTB) structure with the asymmetric motion partition (AMP) mode. the architecture contains two parallel sub-architectures to meet 1080p@30fps real-time video coding. the size L×L of CTB in the architecture is set to L=32 pixels by default, and it can be extended to L=64 and L=16 pixels. A serial mode decision module to find optimal partition mode for the architecture has also been implemented.

关键词： Arrays Very large scale integration Video coding Clocks Motion estimation Encoding

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parallel machine scheduling with a single server: Loading and unloading 1

引用

7th international conference on Combinatorial Optimization and Applications, COCOA 2013

作者： Hu, Jueliang Zhang, Qinghui Dong, Jianming Jiang, Yiwei Department of Mathematics Zhejiang Sci-Tech University Hangzhou310018 China

ISBN: (数字)9783319037806

ISBN: (纸本)9783319037790

this paper addresses the non-preemptive scheduling on two parallel identical machines sharing a single server in charge of loading and unloading jobs. Each job has to be loaded by the server before being processed on one of the machines and unloaded immediately by the server after its processing. the goal is to minimize the makespan. this paper considers classical algorithms LS and LPT for the problem where the loading and unloading times both are equal to one time unit. We first analyze the structure of list scheduling for the problem and then show that the tight worst case ratios of LS and LPT are 12/7 and 4/3, respectively. Finally, we provide a proof of computational complexity for the problem. © Springer international Publishing Switzerland 2013.

关键词： Scheduling

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Rockhopper, a true HPC system built with cloud concepts

Rockhopper, a true HPC system built with cloud concepts

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15th IEEE international conference on Cluster Computing (CLUSTER)

作者： Knepper, Richard Hallock, Barbara Stewart, Craig Link, Matthew Jacobs, Matthew Indiana Univ 2709 E 10th St Bloomington IN 47408 USA Penguin Comp Fremont CA 94538 USA

ISBN: (纸本)9781479908981

A number of services for scientific computing based on cloud resources have recently drawn significant attention in both research and infrastructure provider communities. Most cloud resources currently available lack true high performance characteristics, such as high-speed interconnects or storage. Researchers studying cloud systems have pointed out that many cloud services do not provide service level agreements that may meet the needs of the research community. Furthermore, the lack of location information provided to the user and the shared nature of the systems use may create risk for users of the system, in the instance that their data is moved to an unknown location with an unknown level of security. Indiana University and Penguin Computing have partnered to create a system, Rockhopper, which addresses many of these issues. this system is a true high performance resource, with on-demand allocations, control, and tracking of jobs, situated at Indiana University's high-security datacenter facility. Rockhopper allows researchers to flexibly conduct their work under a number of use cases while also serving as an extension of cyberinfrastructure that scales from the researcher's local environment all the way up through large national resources. We describe the architecture and ideas behind the creation of the system, present a use case for campus bridging, and provide a typical example of system usage. In a comparison of Rockhopper to a cloud-based system, we run the Trinity RNA-seq software against a number of datasets on both the Rockhopper system and on Amazon's EC2 service.

关键词： cloud computing parallel processing scientific information systems security of data software architecture storage management

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Accelerating Applications Using GPUs on Embedded Systems and Mobile Devices

Accelerating Applications Using GPUs on Embedded Systems and...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Miaoqing Huang Chenggang Lai Department of Computer Science and Computer Engineering University of Arkansas Fayetteville AR USA

Graphics processing units (GPUs) are capable of achieving remarkable performance improvements for a broad range of applications. However, they have not been widely adopted in embedded systems and mobile devices as accelerators mainly due to their relatively higher power consumption compared with embedded microprocessors. In this work, we conduct a comprehensive analysis regarding the feasibility and potential of accelerating applications using GPUs in low-power domains. We use two different categories of benchmarks: (1) the Level 3 BLAS subroutines, and (2) the computer vision algorithms, i.e., mean shift image segmentation and scale-invariant feature transform (SIFT). We carried out our experiments on the Nvidia CARMA development kit, which consists of a Nvidia Tegra 3 quad-core CPU and a Nvidia Quadro 1000M GPU. It is found that the GPU can deliver a remarkable performance speedup compared with the CPU while using a significantly less energy for most benchmarks. Further we propose a hybrid approach to developing applications on platform with GPU accelerators. this approach optimally distributes workload between the parallel GPU and the sequential CPU to achieve the best performance while using the least energy.

关键词： Graphics processing units Power demand algorithms Embedded systems Mobile handsets Performance evaluation Image segmentation

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Accelerating Geospatial Applications on Hybrid architectures

Accelerating Geospatial Applications on Hybrid Architectures

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Chenggang Lai Miaoqing Huang Xuan Shi Haihang You CSCE Department University of Arkansas Fayetteville AR USA Department of Geosciences University of Arkansas Fayetteville AR USA National Institute for Computational Sciences University of Tennessee Oak Ridge TN USA

Accelerators have become critical in the process to develop supercomputers with exascale computing capability. In this work, we examine the potential of two latest acceleration technologies, Nvidia K20 Kepler GPU and Intel Many Integrated Core (MIC) Architecture, for accelerating geospatial applications. We first apply a set of benchmarks under 3 different configurations, i.e, MPI+CPU, MPI+GPU, and MPI+MIC. this set of benchmarks include embarrassingly parallel application, loosely communicating application, and intensely communicating application. It is found that the straightforward MPI implementation on MIC cores can achieve the same amount of performance speedup as hybrid MPI+GPU implementation when the same number of processors are used. Further, we demonstrate the potentials of hardware accelerators for advancing the scientific research using an urban sprawl simulation application. the parallel implementation of the urban sprawl simulation using 16 Tesla M2090 GPUs can realize a 155× speedup compared with the single-node implementation, while achieving a good strong scalability.

关键词： Graphics processing units Microwave integrated circuits Benchmark testing Computer architecture Interpolation Geospatial analysis

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Toward automatic optimized code generation for multiprecision modular exponentiation on a GPU

Toward automatic optimized code generation for multiprecisio...

引用

2013 IEEE 37th Annual Computer Software and Applications conference, COMPSAC 2013

作者： Emmart, Niall Weems, Charles Computer Science Department University of Massachusetts Amherst MA 01003-4610 United States

ISBN: (纸本)9780769549798

Multiprocessing modular exponentiation has a variety of uses, including cryptography, prime testing and computational number theory. It is also a very costly operation to compute. GPU parallelism can be used to accelerate these computations, but to use the GPU efficiently, a problem must involve a significant number of simultaneous exponentiation operations. Handling a large number of TLS/SSL encrypted sessions in a data center is a significant problem that fits this profile. We have developed a framework that enables generation of highly efficient NVIDIA PTX implementations of exponentiation operations for different GPU architectures and problem instances. One of the challenges in generating such code is that PTX is not a true assembly language, but is instead a virtual instruction set that is compiled and optimized in different ways for different generations of GPU hardware. thus, the same PTX code runs with different levels of efficiency on different machines. And as the precision of the exponentiation values changes, each architecture has its own break-even points where a different algorithm or parallelization strategy must be employed. To make the code efficient for a given problem instance and architecture thus requires searching a multidimensional space of algorithms and configurations, by generating thousands of lines of carefully constructed PTX code for each combination, executing it, validating the numerical result, and evaluating its actual performance. Our framework automates much of this process, and produces exponentiation code that is up to six times faster than the best known hand-coded implementations. More importantly, the framework enables users to relatively quickly find the best configuration for each new GPU architecture. Our framework is also the basis for the eventual creation of a multiprocessing matrix arithmetic package for GPU cluster systems that will be portable across multiple generations of GPU. © 2013 IEEE.

关键词： Graphics processing unit

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Performance Evaluation of LAMMPS on Multi-core Systems

Performance Evaluation of LAMMPS on Multi-core Systems

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Kwangho Cha National Institute of Supercomputing and Networking Korea Institute of Science and Technology Information Daejeon KOREA

With the widespread use of multi-core processors, specialized applications requiring parallel processing can be run on general desktops. In this study, we measure and analyze the parallel performance of LAMMPS, a classical well-known molecular dynamics code, on single multi-core systems. In order to check the parallel efficiency on single machines, the various types of simulations with LAMMPS were performed with MPI and OpenMP. Although LAMMPS was run on a single machine, MPI based LAMMPS showed higher performance, because LAMMPS has been designed based on MPI and only some part of LAMMPS was parallelized with OpenMP. the preliminary experiments also showed that the memory sub-system affects the performance of LAMMPS.

关键词： Computational modeling Dynamics Software Multicore processing Performance evaluation Force High performance computing

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Genome matching on modern architectures

Genome matching on modern architectures

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international conference on Systems, Signals and Image processing, IWSSIP

作者： Grigore Lupescu Bujor Pavaloiu Faculty of Engineering in Foreign Languages University POLITEHNICA of Bucharest Bucharest Romania BioMedical Engineering Centre University POLITEHNICA of Bucharest Bucharest Romania

Exact string matching algorithms are critical components in computational biology applications regarding the nucleotide or aminoacid sequences. the current paper presents a slightly modified version Boyer-Moore algorithm for string matching (in particular genomes) that has been optimized for a dual Xeon 5860. We highlight several ways to improve execution time and conclude based on our measurements that STTNI hardware instructions alongside core parallelism achieve most of the performance gain.

关键词： Multicore processing Program processors Bioinformatics Genomics Hardware parallel processing

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