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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Efficient implementation of 3780-point FFT on a 16-core processor

Efficient implementation of 3780-point FFT on a 16-core proc...

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international conference on ASIC

作者： Haofan Yang Kedong Chen Shengqiong Xie Ming-e Jing Zhiyi Yu Xiaoyang Zeng State Key Laboratory of ASIC & System Fudan University Shanghai China Shanghai University of Engineering Science

the 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. In this paper, we proposed an efficient implementation for 3780-point FFT on multi-core processors, which makes full use of the parallelism of FFT application and multi-core system. Experiment results demonstrate that multi-core 3780-point FFT implementation not only achieves a speedup ratio of 6.475 over single core implementation but also maintains a great flexibility compared with ASIC implement.

关键词： parallel processing Pipelines Algorithm design and analysis Discrete Fourier transforms Multicore processing Multimedia communication Standards

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Efficient hardware calculation of running statistics

Efficient hardware calculation of running statistics

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international conference on Image and Vision Computing New Zealand, IVCNZ

作者： Donald G. Bailey Michael J. Klaiber School of Engineering and Advanced Technology Massey University Palmerston North Institute for Parallel and Distributed Systems University of Stuttgart

Calculation of mean, variance and standard deviation are often required for segmentation or feature extraction. In image processing, often an integer approximation is adequate. Conventional methods require division and square root operations, which are expensive to realize in hardware in terms of both the amount of required resources and latency. A new class of iterative algorithms is developed based on integer arithmetic. An implementation of the algorithms as a hardware architecture for a Field-Programmable Gate Array (FPGA) is compared with architectures using the conventional approach, which shows a significantly reduced latency while using less hardware resources.

关键词： Hardware Computer architecture Standards Approximation methods Nickel Accuracy Feature extraction

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Towards Adapting parallel Programs to Different Platforms: Identifying Interaction Patterns

Towards Adapting Parallel Programs to Different Platforms: I...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Bogdan Florin Cornea Jaroslaw Slawinski Julien Bourgeois Vaidy Sunderam Emory University Atlanta GA US FEMTO-ST Inst. UFC Besançon France

Modern parallel computing platforms exhibit substantial variation in communication performance between on-socket, on-node and inter-rack locations. When application interaction patterns are irregular, communication-aware process placement on such platforms can be critical for overall runtime. Understanding program interaction patterns can be valuable in order to minimize the impact of capacity variations in communications parameters. Such knowledge can also be useful in selecting the best execution platform from the available options. In this paper we propose an approach based on source code analysis which identifies parallel application communication patterns such as star, ring, mesh, or torus. Our implementation based on ROSE framework was tested on various parallel programs that exhibit different communication patterns. We present the accuracy as well as the limitations of our static identification approach. We envisage augmenting our approach with trace information from pilot runs and best effort approaches to determine a process interaction graph.

关键词： Topology Network topology parallel processing Computer architecture Blood vessels Runtime Object recognition

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Periodic steady state determination of power systems using graphics processing units

Periodic steady state determination of power systems using g...

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international conference on Electrical Engineering, Computing Science and Automatic Control (CCE)

作者： Ernesto Magaña-Lemus Aurelio Medina-Ríos Antonio Ramos-Paz Víctor H. Montesinos-González Facultad de Ingeniería Eléctrica Universidad Michoacana de San Nicolás de Hidalgo (UMSNH) Morelia Michoacán México

Modern advances in computer technology will definitely have a great impact on the methodologies used in the expansion and operational planning of power systems. parallel and distributed systems are the new tendencies in technologies that present a great potential for application in these areas. Graphics processing units (GPUs) have recently become popular in several fields of science due to their capability of performing massively large computational tasks. the use of a GPU for efficiently obtaining the periodic steady state solution in the time domain of large-scale electric power systems with nonlinear components is presented in this paper. Two programming models of the numerical differentiation process are proposed and implemented on a single GPU. the computation time of the simulation performed by co-processing GPU-CPU has been compared with the simulation time required when using a conventional CPU. Several test cases have been analyzed to demonstrate the acceleration of the GPU-CPU simulation and the speed-up achieved.

关键词： Graphics processing units Instruction sets parallel processing Steady-state Power systems Programming Computational modeling

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SPD-RAID4: Splitting Parity Disk for RAID4 Structured parallel SSD Arrays

SPD-RAID4: Splitting Parity Disk for RAID4 Structured Parall...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Wen Pan Feng Liu Tao Xie Yanyan Gao Yiming Ouyang Tian Chen Computer & Information School Hefei University of Technology Hefei Anhui China Computer Science Department San Diego State University San Diego California USA

Data-intensive applications like video processing and bioinformatics increasingly demand a high-performance and highly reliable storage system. Hard disk drive (HDD) has long been used as a standard storage device for most existing storage systems. Recently, NAND-flash memory based solid state drives (SSDs) are gradually exploited to replace HDDs in enterprise computing infrastructures due to their salient features such as high performance, low power consumption, and excellent shock-resistance. With rapid price decreasing and capacity increasing, flash SSD based disk arrays organized in some RAID structures become feasible and greatly needed. In this paper, we propose a new RAID4 architecture called SPD-RAID4 (Splitting Parity Disk - RAID4) for parallel SSD arrays. It splits the parity disk of a traditional RAID 4 array into configurable number of smaller ones. thus, multiple small parity SSDs operate in tandem with data SSDs to achieve a high performance and high level of reliability. We compare the performance of SPD-RAID4 with conventional RAID4 and RAID5 architectures by using both real-world traces and synthetic benchmarks. Experimental results demonstrate that in terms of mean response time SPD-RAID4 outperforms standard RAID5 structured SSD arrays by up to 20.3%. Compared with standard RAID4, SPD-RAID4 achieves a performance gain up to 40.6%.

关键词： Arrays Standards Reliability Time factors Flash memories Performance evaluation

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Constructing Compact Logical Arrays under Flexible Rerouting Schemes

Constructing Compact Logical Arrays under Flexible Rerouting...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Guiyuan Jiang Jigang Wu Jizhou Sun Yiyi Gao School of Computer Science and Technology Tianjin University Tianjin China School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin China Tianjin University Tianjin Tianjin CN

In a multiprocessor array, some processing elements (PEs) fail to function normally due to hardware defects or soft faults caused by overheating, overload or occupancy by other running applications. Fault-tolerant reconfiguration reorganizes fault-free PEs to a logical topology by changing the interconnection among PEs. this paper develops an efficient heuristic algorithm, denoted as CLA, to construct maximum logical array (MLA) with short interconnects under flexible rerouting schemes. In CLA, two MLAs are generated using an existing algorithm FLX, and are then utilized to produce the target logical array. the middle column of the target logical array is generated by forming the straightest column on an area bounded by two logical columns of the two MLAs. Other columns are generated by forming compact columns on relative areas. the problem of finding a compact logical column on an given area is solved by modeling it as a shortest path problem on a directed graph with weights where both vertices and edges of the graph are associated with nonnegative costs. Experimental results validate the efficiency of the the proposed algorithm. For 128 × 128 host arrays with 40% unavailable PEs, the proposed approach improves existing algorithm up to 44% in terms of interconnection length. In addition, the improvement increases with the increasing fault density, implying that CLA is more scalable than the existing algorithm.

关键词： Logic arrays Topology parallel processing Network topology Heuristic algorithms Fault tolerance Fault tolerant systems

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A Comparative Study of Preconditioners for GPU-Accelerated Conjugate Gradient Solver

A Comparative Study of Preconditioners for GPU-Accelerated C...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Yao Chen Yonghua Zhao Wei Zhao Lian Zhao Computer Network Information Center University of Chinese Academy of Sciences Beijing China Computer Network Information Center Chinese Academy of Sciences Beijing China

We compare two types of preconditioners for GPU-Accelerated conjugate gradient solver. For the standard IC preconditioner, we exploit level scheduling to increase multi-thread parallelism of sparse triangular solve on GPU. Meanwhile, we propose a novel reordering technique to maximize the coalescing of global memory accesses. For the approximate inverse preconditioner SSOR-AI, we extend it to second order approximation. Experiments indicate that our IC PCG runs 25% faster than using vendor implementation in CUSPARSE library and SSOR-AI PCG can be twice as fast as IC PCG.

关键词： Graphics processing units Sparse matrices Optimization Integrated circuits Approximation methods parallel processing Linear systems

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High Performance Implementation of ARIA Encryption Algorithm on Graphics processing Units

High Performance Implementation of ARIA Encryption Algorithm...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Limin Xiao Yongnan Li Li Ruan Guangchao Yao Deguo Li School of Computer Science and Engineering Beihang University Beijing China

It becomes increasingly common to use GPU (Graphics processing Units) as accelerators to speed up compute intensive sections of applications. Since block ciphers are supposed to be used for high speed encryption, it is important to implement them as fast as possible. Block cipher ARIA is a new type of encryption standard with four different S-boxes. this paper proposes three methods of high performance implementations of ARIA encryption algorithm on GPU. In order to reduce the data dependency, the round function of ARIA are merged into lookup tables and XOR operations. Encrypting process is performed in parallel and all the data in different GPU memory spaces are arranged properly. Experimental results demonstrate that these techniques accelerate the speed of ARIA encryption significantly. the quantitative performance comparison demonstrates acceleration up to 18 - 45 times speedup while the size of plaintext varies from 4M to 256M.

关键词： Instruction sets Encryption Graphics processing units Indexes Resource management Ciphers Synchronization

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Convergence throughput gain in a unified parallel turbo receiver

Convergence throughput gain in a unified parallel turbo rece...

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international Bhurban conference on Applied Sciences & Technology, IBCAST

作者： Atif Raza Jafri Amer Baghdadi CESAT Islamabad Pakistan TELECOM Bretagne Brest France

ISBN: (纸本)9781467344258

In pursuit of bringing high end applications on radio platforms, recent and evolving wireless standards impose stringent requirements in the shape of high throughputs, error rate performance close to theoretical limits and multi mode transmissions to efficiently use bandwidth in different channel conditions. In the presence of these requirements, the designer comes across contradicting requirements. In fact, in order to handle error rate performance the iterative (Turbo) processing (Turbo/LDPC decoding, Turbo demodulation and Turbo Equalization) is common implementation practice in baseband receivers. However, this creates bottleneck in achieving imposed throughputs. In this scenario, parallelism study and resulting throughput gains while keeping same error rate convergence, provides the designer concrete results to establish compromise among design constraints. In this paper, first of all three level of parallelism study is presented on turbo decoding, turbo demodulation and MIMO turbo equalization. To aid the designer in taking decision during the design, mathematical expressions for throughput gain in unified parallel turbo receiver are provided. throughput gain for different system scenarios are computed by using system parameters and simulation results in derived expressions.

关键词： Decoding parallel processing Vectors throughput Receivers Equalizers MIMO

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General-Purpose Graphics processing Units in Service-Oriented architectures

General-Purpose Graphics Processing Units in Service-Oriente...

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IEEE international conference on Service-Oriented Computing and Applications (SOCA)

作者： Marıa del Carmen Calatrava Moreno thomas Auzinger Technische Universitat Wien Wien Wien AT Institute of Computer Graphics and Algorithms Vienna University of Technology Vienna Austria

Over the last decades, graphics processing units have developed from special-purpose graphics accelerators to general-purpose massively parallel co-processors. In recent years they gained increased traction in high performance computing, as they provide superior computational performance in terms of runtime and energy consumption for a wide range of problems. In this survey, we review their employment in distributed computing for a broad range of application scenarios. Common characteristics and a classification of the most relevant use cases are described. Furthermore, we discuss possible future developments of the use of general purpose graphics processing units in the area of service-oriented architecture. the aim of this work is to inspire future research in this field and to give guidelines on when and how to incorporate this new hardware technology.

关键词： Graphics processing units Hardware Computer architecture Graphics Instruction sets Computational modeling Semiconductor optical amplifiers

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