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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Constructing Compact Logical Arrays under Flexible Rerouting Schemes

Constructing Compact Logical Arrays under Flexible Rerouting...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Guiyuan Jiang Jigang Wu Jizhou Sun Yiyi Gao School of Computer Science and Technology Tianjin University Tianjin China School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin China Tianjin University Tianjin Tianjin CN

In a multiprocessor array, some processing elements (PEs) fail to function normally due to hardware defects or soft faults caused by overheating, overload or occupancy by other running applications. Fault-tolerant reconfiguration reorganizes fault-free PEs to a logical topology by changing the interconnection among PEs. this paper develops an efficient heuristic algorithm, denoted as CLA, to construct maximum logical array (MLA) with short interconnects under flexible rerouting schemes. In CLA, two MLAs are generated using an existing algorithm FLX, and are then utilized to produce the target logical array. the middle column of the target logical array is generated by forming the straightest column on an area bounded by two logical columns of the two MLAs. Other columns are generated by forming compact columns on relative areas. the problem of finding a compact logical column on an given area is solved by modeling it as a shortest path problem on a directed graph with weights where both vertices and edges of the graph are associated with nonnegative costs. Experimental results validate the efficiency of the the proposed algorithm. For 128 × 128 host arrays with 40% unavailable PEs, the proposed approach improves existing algorithm up to 44% in terms of interconnection length. In addition, the improvement increases with the increasing fault density, implying that CLA is more scalable than the existing algorithm.

关键词： Logic arrays Topology parallel processing Network topology Heuristic algorithms Fault tolerance Fault tolerant systems

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A Comparative Study of Preconditioners for GPU-Accelerated Conjugate Gradient Solver

A Comparative Study of Preconditioners for GPU-Accelerated C...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Yao Chen Yonghua Zhao Wei Zhao Lian Zhao Computer Network Information Center University of Chinese Academy of Sciences Beijing China Computer Network Information Center Chinese Academy of Sciences Beijing China

We compare two types of preconditioners for GPU-Accelerated conjugate gradient solver. For the standard IC preconditioner, we exploit level scheduling to increase multi-thread parallelism of sparse triangular solve on GPU. Meanwhile, we propose a novel reordering technique to maximize the coalescing of global memory accesses. For the approximate inverse preconditioner SSOR-AI, we extend it to second order approximation. Experiments indicate that our IC PCG runs 25% faster than using vendor implementation in CUSPARSE library and SSOR-AI PCG can be twice as fast as IC PCG.

关键词： Graphics processing units Sparse matrices Optimization Integrated circuits Approximation methods parallel processing Linear systems

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High Performance Implementation of ARIA Encryption Algorithm on Graphics processing Units

High Performance Implementation of ARIA Encryption Algorithm...

引用

IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Limin Xiao Yongnan Li Li Ruan Guangchao Yao Deguo Li School of Computer Science and Engineering Beihang University Beijing China

It becomes increasingly common to use GPU (Graphics processing Units) as accelerators to speed up compute intensive sections of applications. Since block ciphers are supposed to be used for high speed encryption, it is important to implement them as fast as possible. Block cipher ARIA is a new type of encryption standard with four different S-boxes. this paper proposes three methods of high performance implementations of ARIA encryption algorithm on GPU. In order to reduce the data dependency, the round function of ARIA are merged into lookup tables and XOR operations. Encrypting process is performed in parallel and all the data in different GPU memory spaces are arranged properly. Experimental results demonstrate that these techniques accelerate the speed of ARIA encryption significantly. the quantitative performance comparison demonstrates acceleration up to 18 - 45 times speedup while the size of plaintext varies from 4M to 256M.

关键词： Instruction sets Encryption Graphics processing units Indexes Resource management Ciphers Synchronization

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Convergence throughput gain in a unified parallel turbo receiver

Convergence throughput gain in a unified parallel turbo rece...

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international Bhurban conference on Applied Sciences & Technology, IBCAST

作者： Atif Raza Jafri Amer Baghdadi CESAT Islamabad Pakistan TELECOM Bretagne Brest France

ISBN: (纸本)9781467344258

In pursuit of bringing high end applications on radio platforms, recent and evolving wireless standards impose stringent requirements in the shape of high throughputs, error rate performance close to theoretical limits and multi mode transmissions to efficiently use bandwidth in different channel conditions. In the presence of these requirements, the designer comes across contradicting requirements. In fact, in order to handle error rate performance the iterative (Turbo) processing (Turbo/LDPC decoding, Turbo demodulation and Turbo Equalization) is common implementation practice in baseband receivers. However, this creates bottleneck in achieving imposed throughputs. In this scenario, parallelism study and resulting throughput gains while keeping same error rate convergence, provides the designer concrete results to establish compromise among design constraints. In this paper, first of all three level of parallelism study is presented on turbo decoding, turbo demodulation and MIMO turbo equalization. To aid the designer in taking decision during the design, mathematical expressions for throughput gain in unified parallel turbo receiver are provided. throughput gain for different system scenarios are computed by using system parameters and simulation results in derived expressions.

关键词： Decoding parallel processing Vectors throughput Receivers Equalizers MIMO

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General-Purpose Graphics processing Units in Service-Oriented architectures

General-Purpose Graphics Processing Units in Service-Oriente...

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IEEE international conference on Service-Oriented Computing and Applications (SOCA)

作者： Marıa del Carmen Calatrava Moreno thomas Auzinger Technische Universitat Wien Wien Wien AT Institute of Computer Graphics and Algorithms Vienna University of Technology Vienna Austria

Over the last decades, graphics processing units have developed from special-purpose graphics accelerators to general-purpose massively parallel co-processors. In recent years they gained increased traction in high performance computing, as they provide superior computational performance in terms of runtime and energy consumption for a wide range of problems. In this survey, we review their employment in distributed computing for a broad range of application scenarios. Common characteristics and a classification of the most relevant use cases are described. Furthermore, we discuss possible future developments of the use of general purpose graphics processing units in the area of service-oriented architecture. the aim of this work is to inspire future research in this field and to give guidelines on when and how to incorporate this new hardware technology.

关键词： Graphics processing units Hardware Computer architecture Graphics Instruction sets Computational modeling Semiconductor optical amplifiers

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Application task and data placement in embedded many-core NUMA architectures 13

Application task and data placement in embedded many-core NU...

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10th Workshop on Optimizations for DSP and Embedded Systems, ODES 2013 - In Conjunction with international Symposium on Code Generation and Optimization, CGO 2013

作者： Viring, Karl Lee, Sangheon Cho, Yeongon Ryu, Soojung Egger, Bernhard School of Computer Science and Engineering Seoul National University Korea Republic of Samsung Electronics Samsung Advanced Institute of Technology Korea Republic of

ISBN: (纸本)9781450319058

the advent of many-core chips in the embedded world imposes new challenges to programmers. One of the most important challenges to achieve optimal performance is that the variance in memory access time depending on the issuing core and the location of the data has to be taken into consideration in the already complex environment of parallel applications. In this paper we seek efficient ways of implementing dynamic task and data placement for embedded many-core systems that exhibit NUMA. Achieving a high affinity between a task and its data is desirable to minimize memory access cost and program execution time. this research was carried out using a many-core MPSoC FPGA prototype from Samsung. the MPSoC comprises 16 reconfigurable processors, global SDRAM and distributed scratchpad memory. Since no message passing interface or API's such as OpenMP is available for the Samsung 16-SRP, this paper focuses on optimizations in the application layer. To gain insight into memory performance, a series of micro benchmarks has been carried out. these benchmarks aim at discovering NUMA behavior, memory hierarchy latencies, architecture symmetry, DMA-transfer overhead and congestion. Accessing the SDRAM exhibits NUMA factors up to 1.45, however, the most important factor for achieving high performance is to minimize congestion in the NoC and at the memory controllers. We have applied these findings to two real-world imaging applications, image-blurring and Seeded Region Growing (SRG). the base cases for both applications are parallelized for 16 cores. For image burring, we achieve a 2.75- to 3-fold speedup by distributing the image data to the four SDRAMs and statically assigning the work items to the cores closest to the data. Depending on input image, the SRG application shows a 1.4- to 1.5-fold speedup compared to the base case by applying dynamic work load balancing using hierarchical queues and work-stealing. the results emphasize the importance of considering the underlying

关键词： Message passing

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Greedily using GPU capacity for data list processing in multicore-GPU platforms

Greedily using GPU capacity for data list processing in mult...

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international conference on Electrical Engineering, Computing Science and Automatic Control (CCE)

作者： Carlos Alberto Martínez-Angeles Jorge Buenabad-Chávez Miguel Alfonso Castro-García José Luis Quiroz-Fabián Departamento de Computación CINVESTAV-IPN D.F. México Departamento de Ingeniería Eléctrica D.F México

We have designed data list processing for multicore-GPU platforms and significantly improved the performance of both numerical and symbolic applications. For the latter, a novel aspect of our design was the management and processing of new data dynamically generated within GPUs. this paper presents various optimisations to our first design [1] aimed to use more the GPU, through reducing communication between the host (a multicore) and the GPU, in order to improve performance further. We present experimental results for three applications with different granularities and access patterns. Performance was improved again, significantly in some cases; using multicore-GPU platforms efficiently may involve complex changes to software.

关键词： Graphics processing units Instruction sets Message systems Multicore processing Synchronization Memory management parallel processing

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parallel Map Matching on Massive Vehicle GPS Data Using MapReduce

Parallel Map Matching on Massive Vehicle GPS Data Using MapR...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Jian Huang Shaoqing Qiao Haitao Yu Jinhui Qie Chunwei Liu School of Software Beihang University (BUAA) Beijing China School of Computer Science and Engineering Beihang University (BUAA) Beijing China Beijing Transportation Information Center Beijing China National Space Science Center (NSSC) Chinese Academy of Sciences(CAS) Beijing China

the procedure of matching vehicle location data onto road map is very essential for many ITS (Intelligent Transportation System) applications. However, with the boosting deployment of GPS devices in vehicles, the accumulation of huge amount of GPS data caused great challenge on the efficiency and scalability of traditional serial map matching algorithm. In this paper we address the challenge by presenting a novel parallel map matching algorithm to realize high-performance processing of GPS data. the main idea is to adapt the serial map matching algorithm for cloud computing environment by reforming its' data-intensive or I/O-intensive computing stages using MapReduce paradigm. We implemented the algorithm in Hadoop platform and tested its performance by a large GPS dataset exceeds 120 billion GPS records. Experimental results show that our approach is highly efficient and scalable for massive historical GPS data processing.

关键词： Global Positioning System Roads Computers Vehicles Algorithm design and analysis Sorting

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ParaInsight: An Assistant for Quantitatively Analyzing Multi-granularity parallel Region

ParaInsight: An Assistant for Quantitatively Analyzing Multi...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Ran Ao Guangming Tan Mingyu Chen Institute of Computing Technology Chinese Academy of Sciences Beijing China

With the growing number of cores on chip, scalability of application becomes one of the most important metrics to impact performance and efficient utilization of hardware resource. Simple multi-threading transformation usually acts not well enough so that many of multi-threaded programs should be reconsidered for exploiting more parallelism. However, complex data dependency makes programmer hard to discover the regions with good scalability. Meanwhile, a variety of parallel programming models and platform properties make the choice of parallel granularity even difficult. In this paper, we develop a tool, named Para Insight, to help programmer obtain a quantification insight of parallelism on multi-granularity, as an assistant to ease the process of parallel analysis. We concentrate on revealing the inherent characteristic of program itself, independent of programming model and platform. While regions on which parallelization efforts should be focused are ordering, programmer could choose interested candidate and then use the quantification results to estimate the parallel zing overhead according to concrete parallel programming model and platform parameters. In contrast to many other parallelism discovery tools which mainly focus on parallel zing legacy serial programs, our tool provides assistance on the process of multi-threaded program development. We use multi-threaded benchmark suite Parsec and Splash2 to demonstrate the use of our tool, and specially use two cases to present how to improve performance of multithreaded application with the utilization of analysis data.

关键词： parallel processing Scalability Hardware Measurement Instruction sets Programming Benchmark testing

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On the Performance of Apache Hadoop in a Tiny Private IaaS Cloud

On the Performance of Apache Hadoop in a Tiny Private IaaS C...

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international conference on Information Technology: New Generations (ITNG)

作者： Gabriel Loewen Michael Galloway Susan Vrbsky Department of Computer Science The University of Alabama

ISBN: (纸本)9781467359603

High performance and parallel computing are traditionally implemented on very large dedicated compute clusters. However, as many organizations begin to adopt service-oriented cloud-based infrastructures, we can expect to see the development of parallel computing in the cloud. the goal of a parallel compute cluster is to divide a large job into several small jobs, execute the small jobs in parallel on many compute nodes, and then combine the results in some coherent manner. the biggest hurdle in moving this type of service to a cloud-based infrastructure is that performance will undoubtedly be affected by many factors, particularly those related to virtualization in clouds, such as memory and CPU overhead, limited resources, and others relating to hardware virtualization. In order to fully understand how virtualization can affect parallel computing in a tiny private cloud, we have devised four case studies that examine the performance of Apache Hadoop in varying environments on our private cloud. Our case studies are comprised of a baseline or bare metal (non-virtualized) cluster deployment consisting of seven nodes, a seven-node virtual machine cluster, a twenty-node virtual machine cluster, and an optimized seven-node virtual machine cluster. Results show that, although small data sets result in comparable job completion times, as the data size increases the performance of Apache Hadoop is affected greatly by virtualization even when we attempt to optimize the configuration of our cloud.

关键词： Virtual machining Cloud computing Virtualization Metals Hardware parallel processing Organizations

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