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Performance Model for Master/Worker Hybrid Applications on Multicore Clusters

Performance Model for Master/Worker Hybrid Applications on M...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Abel Castellanos Andreu Moreno Joan Sorribes Tomàs Margalef Departament Arquitectura de Computadors i Sistemes Operatius Universitat Autònoma de Barcelona Spain Escola Universitaria Salesiana de Sarria Barcelona Spain

there are several parallel applications that are implemented using a Master/Worker parallel/distributed programming paradigm. Applications using this predefined programming structure can be easily implemented using message passing programming libraries (MPI). Moreover, the multicore features present nowadays on CPU architecture can be exploited at the node level by applying thread parallelism (OpenMP). In order to exploit the benefits of both two levels of parallelism, the Master/Worker applications can be implemented as hybrid applications. However, reaching the expected performance indexes is not trivial because there are several parameters (number of nodes, number of threads per node, thread affinity and data distribution among all nodes) that must be tuned for each particular application or even during its execution to reach a successful performance. On the other hand, the application workload may change drastically during successive executions, so those parameters need to be modified according to this behavior. Additionally, cache memory architecture in multicore systems directly influences the performance and this behaviour must be deeply analysed. In this paper we present a proposal to model the performance of hybrid Master/Worker applications on multicore systems considering the issues outlined above. In particular, this model determines dynamically at runtime the configuration of the appropriate number of workers and threads of the hybrid application to achieve the best possible performance.

关键词： Computational modeling Multicore processing Message systems Predictive models Mathematical model Data models

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Two exact methods for mapping on heterogeneous CPU/FPGA architectures

Two exact methods for mapping on heterogeneous CPU/FPGA arch...

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IEEE international conference on Networking, Sensing and Control

作者： Omar Souissi Artiba Abdelhakim LAMIH UMR 8201 University of Valenciennes and Hainaut-Cambrésis Valenciennes France

ISBN: (纸本)9781467351980

this research investigates the problem of the optimisation of static task mapping on a heterogeneous computing system CPU/FPGA (Central processing Unit/Field-Programmable Gate Array) used to implement intimately coupled hardware and software models. In the face of obstacles as memory-wall, power wall and real-time requirements, hardware designers are directed more and more towards reconfigurable computing. the use of heterogeneous CPU/FPGA systems is one of the most promising solutions in order to increase the performance. Indeed, in such systems, multi-core processors (CPU) provide high computation rates while the reconfigurable logic (FPGA) offers high performance and adaptability to the application real-time constraints. However, heterogeneous computing systems present new challenges, and one of the most important issues is how to map efficiently the application tasks on the available resources while considering real-time constraints. this work includes the development of two exact methods that focus on the static initial task mapping, for two different case studies. In the first case, the execution is considered preemptive and the problem of task mapping is treated in terms of workload on the heterogeneous system. While in the second case the execution is considered non preemptive and the main objective is to minimize the makespan. In both case studies we consider communication constraints, since the application tasks are linked by precedence.

关键词： Logic gates Computational modeling Program processors Field programmable gate arrays

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Automatic Mapping Single-Device OpenCL Program to Heterogeneous Multi-device Platform

Automatic Mapping Single-Device OpenCL Program to Heterogene...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Dong Chen Changqing Xun Dafei Huang Mei Wen Chunyuan Zhang National Key Laboratory of Parallel and Distributed Processing

In this paper, we propose a framework to automatically map single-device OpenCL programs to heterogeneous multi-device platforms with performance concerns. Our framework is based on the independence of work groups which built inside the OpenCL programming model and relies heavily on the knowledge of global memory access regions of work groups. So global memory access patterns of work groups are analyzed and an abstract representation CCRwS is designed to describe the exact memory access regions of each memory access statement in the kernels. A global memory access analyzer is designed to get CCRwSs by performing static program analysis on kernel codes. Based on CCRwSs, data transfer between multiple devices and host can be fully controlled by our framework. then a kernel code regenerator is designed to distribute the workload and perform architecture specific optimizations by code transformation. then we tested our framework on a platform with 2 Intel E5-2650 CPUs and 4 NVIDIA Tesla C2050 GPUs. Compared with the performance on single GPU, the kernels running on all the 6 devices can achieve about 4.5x faster.

关键词： Kernel Indexes Performance evaluation Benchmark testing Abstracts Optimization Computer architecture

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Correlation Analysis of Multivariate Neural Signals with Massively parallel Wavelet Coherence

Correlation Analysis of Multivariate Neural Signals with Mas...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Weizhou Peng Yangyang Hu Ke Zeng Xiaodao Chen Dan Chen Haiqing Chen Jiaqin Yan Xiaoli Li China University of Geosciences Wuhan Hubei CN Sch. of Comput. Sci. China Univ. of Geosci. Wuhan China Beijing Normal University Beijing Beijing CN

the study of the correlations that may exist between neural signals generated by different brain regions is a critical issue in understanding brain functions. there is a lack of an appropriate approach which is capable of (1) estimating the correlation between neural signals, and (2) adapting to the quickly increasing scales and sizes of neural signals. Wavelet coherence is an effective method for investigating the interaction dynamics between neuronal oscillations. Continuous wavelet transform (CWT) is suitable for analyzing neural signals which are non-stationary in nature. CWT forms the basis of wavelet coherence methods. However, the wavelet coherence method has been largely hampered by the high complexity of CWT. Aiming at this problem, this study proposed an improved wavelet coherence method with parallelized wavelet transform upon General-purpose computing on the graphic processing unit (GPGPU), namely, GPGPU-enabled wavelet coherence (GWC). the proposed method has been used to analyze 32-channel ERP recordings. the experimental results indicate that (1) the correlation between different neural signals can successfully indicate the different reactions of brain regions when people are watching videos and (2) GWC solves the performance bottleneck with the conventional counterparts.

关键词： Coherence Fourier transforms Continuous wavelet transforms Correlation Graphics processing units

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An Efficient, QoS-Aware I/O Scheduler for Solid State Drive

An Efficient, QoS-Aware I/O Scheduler for Solid State Drive

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Quan Zhang Dan Feng Fang Wang Yanwen Xie Wuhan National Laboratory for Optoelectronic Huazhong University of Science & Technology Wuhan China

Flash-based solid-state drive has been proved to be a competitive alternative to mechanical disk for its high performance and low power consumption. But SSD still suffers from relatively high price and low density, which calls for consolidating device resource to bring down the cost of deploying expensive dedicated flash-based storage systems for specific applications. Within such environment, applications may compete for storage service and interfere with each other. therefore, storage service providers must ensure performance isolation. However, current research mainly focuses on performance guarantees on mechanical disk. In this paper, we present a 2-level scheduling framework where the higher level targets performance isolation through distinguishing the cost of read and write operations in SSD, and the lower level builds channel-based queues for SSD to exploit the inherent parallelism of SSD. Synthetic and real workloads are used in our evaluation to demonstrate the effectiveness of our 2-level scheduling framework, and the results show it outperforms other I/O schedulers at both aspects of performance isolation and I/O efficiency.

关键词： Performance evaluation Quality of service parallel processing Ash Resource management throughput Equations

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CLSIFT: An Optimization Study of the Scale Invariance Feature Transform on GPUs

CLSIFT: An Optimization Study of the Scale Invariance Featur...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Weiyan Wang Yunquan Zhang Long Guoping Shengen Yan Haipeng Jia School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computing Science Institute of Software Chinese Academy of Sciences Lab. of Parallel Software and Computational Science Institute of Software Chinese Academy of Sciences

Scale Invariance Feature Transform (SIFT) is quite suitable for image matching because of its invariance to image scaling, rotation and slight changes in illumination or viewpoint. However, due to high computation complexity it's technically challenging to deploy SIFT in real time application situations. To address this problem, we propose CLSIFT, an OpenCL based highly speeded up and performance portable SIFT solution. Important optimization techniques employed in CLSIFT such as: (1) For less global memory traffic, independent logical functions are merged into the same kernel to reuse data. (2) loop buffers are introduced in for data and intermediate results reusing. (3)Task queue used to schedule threads in the same branch to remove branch divergences. (4) Data partition is based on the statics patterns for workload balance among workgroups. (5) Overlap of CPU time and better parallel strategies are used too. With all mentioned efforts, CLSIFT processes lena. jpg at 74.2 FPS and 43.4FPS respectively on NVidia and AMD GPUS, much higher than CPU's nearly 10 FPS and the known fastest SIFTGPU's 39.8 FPS and 13FPS. Moreover in a quantitative comparison approach we analyze those successful strategies beating SIFTGPU, a famous existing GPU implementation. Additionally, we observe and conclude that NVidia GPU achieves better occupancy and performance due to some factors. Finally, we summarize some techniques and empirical guiding principles that may be shared by other applications on GPU.

关键词： Graphics processing units Instruction sets Kernel Accuracy Histograms Optimization Memory management

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Scaling HPC Clusters with volunteer computing for data intensive applications

Scaling HPC Clusters with volunteer computing for data inten...

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international Joint conference on Computer Science and Software Engineering (JCSSE)

作者： Ekasit Kijsipongse Suriya U-ruekolan Large-Scale Simulation Research Laboratory National Electronics and Computer Technology Center Klong Luang Pathum thani Thailand

ISBN: (纸本)9781479908059

Due to the computational demand of data intensive applications, parallel computer hardware such as the HPC Cluster system is required to execute such the applications. However, building large HPC Clusters for this sole purpose is not always feasible or even not cost-effective since the purchasing, operational and maintenance cost of' the dedicated systems is too high but they are not fully utilized in most of the time. In this regard, Volunteer Computing can address this problem as it provides a large amount of computing resources at no cost. We develop a system that expands the computing capability of HPC Clusters by using the additional computing power donated by volunteer users who would like to give the computing resources of their unused desktop computers to help execute jobs in the HPC Clusters. the proposed system can combine the native Cluster compute nodes and a set of' non-dedicated compute nodes contributed by volunteers. the experiments demonstrate that the volunteer resources, such as CPU time, disk storage and GPU, can be seamlessly integrated into the HPC Clusters allowing the systems to dynamically scale up/down regarding to the amount of resources in Volunteer Computing.

关键词： Logic gates Graphics processing units Information services Electronic publishing Internet Torque

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MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

MPSoC architecture for H.264/AVC intra prediction chain on S...

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international conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： N. Belhadj M. Turki Z. Marrakchi M. Ali Ben Ayed N. Masmoudi H. Mehrez Laboratory of Electronics and Technology of Information from the National Engineering University of Sfax Tunisia Laboratory of Computer Sciences LIP6 University of Pierre and Marie Curie Paris France

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level parallelism (DLP) partitioning. this architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

关键词： Computer architecture Program processors Video coding Encoding Field programmable gate arrays parallel processing Partitioning algorithms

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Device View Redundancy: an adaptive low-overhead fault tolerance mechanism for many-core system

Device View Redundancy: an adaptive low-overhead fault toler...

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international Workshop on Intelligent Communication and Social Networks

作者： Wentao Jia Chunyuan Zhang Jian Fu National Key Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Institute for Informatics University of Amsterdam

ISBN: (纸本)9781479909735

Continued increasing of fault rate in integrate circuit makes processors more susceptible to errors, especially many-core processor. Meanwhile, most systems or applications do not need full fault coverage, which has excessive overhead. So on-demand fault tolerance is desired for these applications. In this paper, we propose an adaptive low-overhead fault tolerance mechanism for many-core system, called Device View Redundancy (DVR). It treats fault tolerance as a device that can be configured and used by application when high reliability is needed. Nevertheless, DVR exploits the idle resources for low-overhead fault tolerance, which is based on the observation that the utilization of many-core system is low due to lack of parallelism in application. Finally, the experiment shows that the performance overhead of DVR is reduced by 16% to 98% compared with full Dual Modular Redundancy (DMR).

关键词： On-demand redundancy Idle resource exploitation Dynamic coupling Low-overhead Many core system

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Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation

Design of a multi GBPS Single Carrier digital baseband for 6...

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international conference on Field Programmable Logic and Applications

作者： Surendra Guntur Feike Jansen Jan Hoogerbrugge Lotfi Abkari Eric Vos NXP Semiconductors Eindhoven Netherlands NXP Semiconductors Leuven Belgium

this paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. the baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. the demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beam-forming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using π/2 QPSK modulation with a 13/16 LDPC code rate.

关键词： Baseband Field programmable gate arrays Receivers throughput Radio frequency parallel processing Application specific integrated circuits

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