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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Design and Implementation of a parallel Priority Queue on Many-core architectures

Design and Implementation of a Parallel Priority Queue on Ma...

引用

19th international conference on High Performance Computing (HiPC)

作者： He, Xi Agarwal, Dinesh Prasad, Sushil K. Georgia State Univ Dept Comp Sci Atlanta GA 30303 USA

ISBN: (纸本)9781467323703;9781467323727

An efficient parallel priority queue is at the core of the effort in parallelizing important non-numeric irregular computations such as discrete event simulation scheduling and branch-and-bound algorithms. GPGPUs can provide powerful computing platform for such non-numeric computations if an efficient parallel priority queue implementation is available. In this paper, aiming at fine-grained applications, we develop an efficient parallel heap system employing CUDA. To our knowledge, this is the first parallel priority queue implementation on many-core architectures, thus represents a breakthrough. By allowing wide heap nodes to enable thousands of simultaneous deletions of highest priority items and insertions of new items, and taking full advantage of CUDA's data parallel SIMT architecture, we demonstrate up to 30-fold absolute speedup for relatively fine-grained compute loads compared to optimized sequential priority queue implementation on fast multicores. Compared to this, our optimized multicore parallelization of parallel heap yields only 2-3 fold speedup for such fine-grained loads. this parallelization of a tree-based data structure on GPGPUs provides a roadmap for future parallelizations of other such data structures.

关键词： data structures graphics processing units multiprocessing systems parallel architectures queueing theory

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ReKonf: A reconfigurable adaptive ManyCore architecture

ReKonf: A reconfigurable adaptive ManyCore architecture

引用

2012 10th IEEE international Symposium on parallel and Distributed processing with Applications, ISPA 2012

作者： Pal, Rajesh Kumar Paul, Kolin Prasad, Sanjiva Indian Institute of Technology Delhi India

ISBN: (纸本)9780769547015

the "one-architecture-fits-all" design philosophy is inadequate for catering to the diverse characteristics of applications running on manyCore architectures. After evaluating various configurations of manyCore architectures for a variety of applications, we designed ReKonf, a reconfigurable adaptive manyCore architecture. ReKonf dynamically configures its reconfigurable components to morph into significantly different configurations on the same architecture by continuously monitoring vital parameters of applications. ReKonf adapts the architecture by tracking core utilization, live cache utilization and cache sharing between threads, at runtime without losing execution state. Our evaluation of various applications on a cycle accurate simulator shows that the (reconfigurable) architecture suitable for such applications can be classified into three main variants: Chip Multiprocessor mode;Symmetric Multiprocessor mode;and Clustered mode, with up to 256 processing cores. Our results show that improvements from 32% to 72% over a baseline configuration can be observed by choosing the right configuration for an application. We also propose architecture components that should be reconfigurable in future manyCore architectures. © 2012 IEEE.

关键词： Reconfigurable architectures

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GrABFAST: A CUDA based GPU Accelerated Fast Short Sequence Alignment Algorithm

GrABFAST: A CUDA based GPU Accelerated Fast Short Sequence A...

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19th international conference on High Performance Computing (HiPC)

作者： Narang, Ankur Soman, Jyothish Lahabar, Sheetal IBM India Res Labs Vasant Kunj Delhi 110070 India

ISBN: (纸本)9781467323703;9781467323727

Next Generation Sequencing (NGS) platforms typically produce short reads of size 50-150 base pairs (bp). the number of such short reads can be up to 6 billion per run. To align these short reads to a large genome is a computationally challenging problem. In this paper, we address this problem by considering the design and optimization of parallel sequence alignment on GPU based hybrid architectures. Even though the sequence alignment algorithm is inherently data-parallel, issues such as (a) space-time trade-offs in the Indexing schema, (b) need for fast candidate location search (CAL) on GPU, (c) maintaining low divergence along with low space for the dynamic programming based local alignment, make this a very challenging problem. We present the design of our novel parallel algorithm Graphics processor Accelerated BFAST (GrABFAST) for large scale read alignment that overcomes these challenges and demonstrates superior performance compared to Intel multicore architectures. Using 5 large genomes including those of Humans, Maize, Horse, Dog and Bacteria, we demonstrate a speedup of around 6x using Fermi Tesla C2070 GPUs vs the BFAST algorithm on 16 core Intel Xeon 5570 architecture.

关键词： dynamic programming graphics processing units multiprocessing systems parallel algorithms parallel architectures

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Application specific hardware architecture for high-throughput short-length LDPC decoders

Application specific hardware architecture for high-throughp...

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IEEE international conference on Intelligent Computer Communication and processing

作者： Bogdan Belean Sergiu Nedevschi Monica Borda National Institute for R&D of Isotopic and Molecular Technologies INCDTIM Computer Science Dept. Technical University of Cluj-Napoca Communication Dept. Technical University of Cluj-Napoca

ISBN: (纸本)9781479914920

LDPC codes have been intensively used in various wireless communication applications, due to their increased BER performance. the present paper summarizes the state of the art applications of short length LDPC codes and proposes FPGA based application specific hardware architectures for short-length LDPC decoders. the decoding algorithms considered for implementation are both belief propagation and min-sum algorithm. Due to the increased BER performances, the proposed architecture make use of parallel computation capabilities offered by FPGA technology in order to implement the belief propagation algorithm. In spite of the iterative nature and increased computational complexity of the LDPC decoding algorithm, the proposed architecture achieves high-throughput, mandatory in real-time application and data transmission. the architecture for the LDPC belief propagation based decoder is based on arctangent hyperbolic function approximation used for check nodes update.

关键词： LDPC codes FPGA Decoding algorithms Hardware implementations parallel computing

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parallel parameter identification in industrial biotechnology

Parallel parameter identification in industrial biotechnolog...

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2012 10th IEEE international Symposium on parallel and Distributed processing with Applications, ISPA 2012

作者： Baumann, thomas Resch, Michael University of Stuttgart 70550 Stuttgart Germany

ISBN: (纸本)9780769547015

Real-valued black-box optimization of badly behaved and not well understood functions is a wide topic in many scientific areas. Possible applications range from maximizing portfolio profits in financial mathematics over efficient training of neuronal networks in computational linguistics to parameter identification of metabolism models in industrial biotechnology. this paper presents a comparison of several global as well as local optimization strategies applied to the task of efficiently identifying free parameters of a metabolic network model. A focus is being set on the ease of adopting these strategies to modern, highly parallel architectures. Finally an outlook on the possible parallel performance is being presented. © 2012 IEEE.

关键词： Optimization

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Efficient GPU-Based Algorithm for Aligning Huge Sequence Database

Efficient GPU-Based Algorithm for Aligning Huge Sequence Dat...

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international Workshop on Intelligent Communication and Social Networks

作者： Chun-Yuan Lin Che-Lun Hung Jen-Cheng Huang Dept. Computer Science and Information Engineering Chang Gung University Dept. Computer Science and Communication Engineering Providence University

ISBN: (纸本)9781479909735

Sequence alignment has been widely utilized in biological computing science. To obtain the optimal alignment results many algorithms adopts dynamic programming method to achieve this goal. Smith-Waterman algorithm is the famous in the sequence alignment approach. However, such dynamic programming algorithms are computation-consuming. It is impossible to use these algorithms to compare query sequence with a sequence database such as GenBank and PDB. Recently, GPU computing has been applied in many sequence alignment algorithms to enhance the performance. In this paper, we proposed a GPU-based Smith-Waterman algorithm by combining the CPU and GPU computing capabilities to accelerate alignments on a sequence database. In the proposed algorithm, a filtration mechanism using frequency distance is used to decrease the number of compared sequences. We implemented the Smith-Waterman alignments by CUDA on the NVIDIA Tesla C2050. the experimental results show that the highest speedup ratio is about 80 to 90 times over CPU-based Smith-Waterman algorithm.

关键词： Sequence alignment Smith-Waterman algorithm GPU parallel processing

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Optimization techniques and performance analyses of two life science algorithms for novel GPU architectures

Optimization techniques and performance analyses of two life...

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20th Euromicro international conference on parallel, Distributed and Network-Based processing, PDP 2012

作者： Dilch, David Mehofer, Eduard Research Group Scientific Computing Faculty of Computer Science University of Vienna Austria

ISBN: (纸本)9780769546339

In this paper we evaluate two life science algorithms, namely Needleman-Wunsch sequence alignment and Direct Coulomb Summation, for GPUs. Whereas for Needleman-Wunsch it is difficult to get good performance numbers, Direct Coulomb Summation is particularly suitable for graphics cards. We present several optimization techniques, analyze the theoretical potential of the optimizations with respect to the algorithms, and measure the effect on execution times. We target the recent NVIDIA Fermi architecture to evaluate the performance impacts of novel hardware features like the cache subsystem on optimizing transformations. We compare the execution times of CUDA and OpenCL code versions for Fermi and predecessor models with parallel OpenMP versions executed on the main CPU. © 2012 IEEE.

关键词： Graphics processing unit

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parallelization strategies of the canny edge detector for multi-core CPUs and many-core GPUs

Parallelization strategies of the canny edge detector for mu...

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2012 IEEE 10th international New Circuits and Systems conference, NEWCAS 2012

作者： Cheikh, Taieb Lamine Ben Beltrame, Giovanni Nicolescu, Gabriela Cheriet, Farida Tahar, Sofiène Department of Computer Science Ecole Polytechnique de Montréal Montréal Canada Department of Electrical and Computer Engineering Concordia University Montréal Canada

ISBN: (纸本)9781467308595

In this paper we study two parallelization strategies (loop-level parallelism and domain decomposition), and we investigate their impact in terms of performance and scalability on two different parallel architectures. As a test application, we use the Canny Edge Detector due to its wide range of parallelization opportunities, and its frequent use in computer vision applications. Different parallel implementations of the Canny Edge Detector are run on two distinct hardware platforms, namely a multi-core CPU, and a many-core GPU. Our experiments uncover design rules that, depending on a set of applications and platform factors (parallel features, data size, and architecture), indicate which parallelization scheme is more suitable. © 2012 IEEE.

关键词： parallel architectures

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Active Power Filters Compensator Implementation Using parallel Structures in FPGA Devices

Active Power Filters Compensator Implementation Using Parall...

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10th IEEE/IAS international conference on Industry Applications (INDUSCON)

作者： Lopes, Alexsandro B. Favarim, Fabio Carati, Emerson G. Univ Tecnol Fed Parana Elect Engn Postgrad Program PPGEE UTFPR BR-85503390 Pato Branco PR Brazil

ISBN: (纸本)9781467324120

this paper presents a parallel implementation approach of selective harmonic compensator for active power filters. this approach uses field programmable gate array (FPGAs) in order to reduce the compensator computational time. To compensate for even a small number of harmonics digital filters require multiple calculation instructions involving multiplications and additions. thus, to improve the performance of the computer system it is proposed the digital compensator implementation using parallel structures in FPGA devices. Experimental results are presented to compare the speedup of the proposed parallel approach with the DSP sequential execution time conventionally used in active power filters applications.

关键词： Active Power Filters Digital Control FPGA Devices parallel processing

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Solution of Identification Problems in Computational Mechanics - parallel processing Aspects

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10th Nordic international conference on Applied parallel Computing - State of the Art in Scientific and parallel Computing (PARA)

作者： Blaheta, Radim Kohut, Roman Jakl, Ondrej Acad Sci Czech Republic Inst Geon Ostrava 70800 Czech Republic

ISBN: (纸本)9783642281440

Problems of identification of material parameters (mostly parameters appearing in constitutive relations) have applications in many fields of engineering including investigation of processes in a rock mass. this paper outlines the structure of parameter identification problems, methods for their solution and describes an identification (calibration) problem from geotechnics, which will serve as a realistic benchmark problem for illustration of the behaviour of selected parameter identification methods.

关键词： inverse problems identification of material parameters Nelder-Mead method genetic algorithms rock mechanics

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