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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2792 条记录，以下是191-200 订阅

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Towards Efficient Execution of Erasure Codes on Multicore architectures

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10th Nordic international conference on Applied parallel Computing - State of the Art in Scientific and parallel Computing (PARA)

作者： Wyrzykowski, Roman Kuczynski, Lukasz Wozniak, Marcin Czestochowa Tech Univ Inst Comp & Informat Sci PL-42201 Czestochowa Poland

ISBN: (纸本)9783642281440;9783642281457

Erasure codes can improve the availability of distributed storage in comparison with replication systems. In this paper, we focus on investigating how to map systematically the Reed-Solomon and Cauchy Reed-Solomon erasure codes onto the Cell/B.E. and GPU multicore architecture. A method for the systematic mapping of computation kernels of encoding/decoding algorithms onto the Cell/B.E. architecture is proposed. this method takes into account properties of the architecture on all three levels of its parallel processing hierarchy. the performance results are shown to be very promising. the possibility of using GPUs is studied as well, based on the Cauchy version of Reed-Solomon codes.

关键词： Erasure codes Reed-Solomon codes Cauchy Reed-Solomon codes multicore architectures Cell/BE GPU

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Fast and parallel Computation of the Discrete Periodic Radon Transform on GPUs, multi-core CPUs and FPGAs 25

Fast and Parallel Computation of the Discrete Periodic Radon...

引用

25th IEEE international conference on Image processing (ICIP)

作者： Carranza, Cesar Pattichis, Marios Llamocca, Daniel Pontificia Univ Catolica Peru Secc Elect & Elect Lima 32 Peru Univ New Mexico Dept Elect & Comp Engn Albuquerque NM 87131 USA Oakland Univ Dept Elect & Comp Engn Rochester MI 48063 USA

ISBN: (纸本)9781479970612

the Discrete Periodic Radon Transform (DPRT) has many important applications in reconstructing images from their projections and has recently been used in fast and scalable architectures for computing 2D convolutions. Unfortunately, the direct computation of the DPRT involves O(N-3) additions and memory accesses that can be very costly in single-core architectures. the current paper presents new and efficient algorithms for computing the DPRT and its inverse on multi-core CPUs and GPUs. the results are compared against specialized hardware implementations (FPGAs/ASICs). the results provide significant evidence of the success of the new algorithms. On an 8-core CPU (Intel Xeon), with support for two threads per core, FastDirDPRT and FastDirInvDPRT achieve a speedup of approximately 10x (up to 12:83x) over the single-core CPU implementation. On a 2048-core GPU (GTX 980), FastRayDPRT and FastRayInvDPRT achieve speedups in the range of 526 (for 127 x 127) to 873 (for 1021 x 1021), which approximate ideal speedups of what can be achieved. the DPRT can be computed exactly and in real-time (30 frames per second) for 1471x1471 images using FastRayDPRT on the GPU. Furthermore, the GPU algorithms approximate the performance of an efficient FPGA implementation using 2N parallel cores at 100MHz.

关键词： Discrete Periodic Radon Transform parallel Architecture Multi-core CPU GPU FPGA

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Wireless Bluetooth Communications Combine with Secure Data Transmission Using ECDH and conference Key Agreements

Wireless Bluetooth Communications Combine with Secure Data T...

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10th international conference on algorithms and architectures for parallel processing

作者： Lin, Hua-Yi Chiang, Tzu-Chiang China Univ Technol Dept Informat Management Hu Kou Taiwan Tunghai Univ Dept Informat Management Taichung Taiwan

ISBN: (纸本)9783642131189

As the fast development of Bluetooth networks and wireless communications, the mobile devices share information with each other easier than ever before. However, the handy communication technology accompanies privacy and security issues. Nowadays, a Bluetooth adopts peer-to-peer and Frequency Hopping Spread Spectrum (FHSS) mechanisms to avoid data reveal, but the malicious attacks collect the transmission data of the relay station for a long period of time and then can break into the system. In this study, we take a Piconet as a cube, and transform a Scatternet into a cluster (N-cube) structure. Subsequently, this study exploits the Elliptic Curve Diffie-Hellman (ECDH) [1] and the conference Key (CK) schemes to perform session key agreements and secure data transmissions. the proposed scheme only needs a small key length 160-bit to achieve compatible security levels on 1024-bit Diffee-Hellman (DH) [2], and each node uses few CPU, memory and bandwidth to complete security operations. As a result, the proposed fault-tolerant routing algorithm with secure data transmissions can perform rapidly and efficiently, and is quite suited for Bluetooth networks with limited resources.

关键词： Bluetooth FHSS Piconet Scatternet ECDH CK DH

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A parallel global-local mixed evolutionary algorithm for multimodal function optimization 5

A parallel global-local mixed evolutionary algorithm for mul...

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5th international conference on algorithms and architectures for parallel processing

作者： Wu, ZJ Kang, LS Zou, XF Wuhan Univ State Key Lab Software Engn Wuhan 430072 Peoples R China

ISBN: (纸本)0769515126

this paper presents a two-level parallel evolutionary algorithm for solving function optimization problem containing multiple solutions.. By combining the characteristics of both global search and local search, the former enables individual to draw closer to each optimal solution and keeps the genetic diversity,of individuals. then different individuals are selected fort local evolution in their appropriate neighborhood. this simple as well as easy-to-handle algorithm turns out to be very practical according to the numerical experiments which indicate that all optimal solutions can be found out by running once of the algorithm within a fairly short period of time.

关键词： Evolutionary algorithms

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Balanced Multi-process parallel Algorithm for Chemical Compound Inference with Given Path Frequencies

Balanced Multi-process Parallel Algorithm for Chemical Compo...

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10th international conference on algorithms and architectures for parallel processing

作者： Zhou, Jiayi Yu, Kun-Ming Lin, Chun Yuan Shih, Kuei-Chung Tang, Chuan Yi Chung Hua Univ Dept Comp Sci & Informat Engn Hsinchu 300 Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30013 Taiwan Chang Gung Univ Dept Comp Sci & Informat Engn Taoyuan Taiwan

ISBN: (纸本)9783642131356

To enumerate chemical compounds with given path frequencies is a fundamental procedure in Chemo- and Bio-inforrnatics. the applications include structure determination, novel molecular development, etc. the problem complexity has been proven as NP-hard. Many methods have been proposed to solve this problem. However, most of them are heuristic algorithms. Fujiwara et al. propose a sequential branch-and-bound algorithm. Although it reaches all solutions and avoids exhaustive searching, the computation time still increases significantly when the number of atoms increases. Hence, in this paper, a parallel algorithm is presented for solving this problem. the experimental results showed that computation time was reduced even when more processes were launched. Moreover, the speed-up ratio for most of the test cases was satisfactory and, furthermore, it showed potential for use in drug design.

关键词： Branch-and-bound algorithm load-balancing chemical compound inference drug design

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parallelIZATION OF COMPUTER VISION algorithms ON A RECONFIGURABLE MULTIPROCESSOR 12

PARALLELIZATION OF COMPUTER VISION ALGORITHMS ON A RECONFIGU...

引用

conference C on Signal processing and conference D on parallel Computing, at the 12th IAPR international conference on Pattern Recognition

作者： BHANDARKAR, SM ARABNIA, HR UNIV GEORGIA DEPT COMP SCIATHENSGA 30602

ISBN: (纸本)0818662751

A novel reconfigurable architecture based on a Multi-Ring Multiprocessor Network is described. the reconfigurable architecture is shown to combine low network diameter with a low degree of connectivity for each node in the network. the mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. A large class of algorithms for the Boolean n-cube and the 2-D mesh is shown to map efficiently on the proposed architecture without loss of performance. the architecture is shown to be well suited for a number of problems in computer vision. © 1994 IEEE.

关键词： Reconfigurable architectures

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Design of Unified Support Vector Machine Circuit for Pedestrians and Cars Detection

Design of Unified Support Vector Machine Circuit for Pedestr...

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10th IEEE international New Circuits and Systems conference (NEWCAS)

作者： Kim, Soojin Lee, Seonyoung Min, Kyoungwon Cho, Kyeongsoon Hankuk Univ Foreign Studies Dept Elect & Informat Engn Yongin South Korea Korea Elect Technol Inst SoC Platform Res Ctr Sungnam South Korea

ISBN: (纸本)9781467308595

this paper describes the design of unified support vector machine circuit for pedestrians and cars detection. By unifying the algorithms and architectures of linear and nonlinear SVM classifications, the proposed circuit can support both linear and non-linear classifications very efficiently in terms of circuit size and performance. the circuit size is minimized by sharing most of the resources required in the computation for both classification types. parallel architecture with pipeline is adopted to accelerate the processing speed to handle a large amount of operations for real-time processing. 48x96 and 64x64 sliding windows with 6 window strides are used to detect pedestrians and cars, respectively. the synthesized circuit using 65nm standard cell library consists of 848,349 gates and its maximum operating frequency is 435MHz. the circuit can process 91.9 640x480 image frames per second assuming three cameras equipped on front, right and left side positions of the vehicle.

关键词： Pedestrians Cars Support Vector Network maximum operating frequency ARCHITECTURE processing SPEED Building construction pipeline Linear

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A coarse grained parallel algorithm for Hausdorff Voronoi diagrams

A coarse grained parallel algorithm for Hausdorff Voronoi di...

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35th international conference on parallel processing

作者： Dehne, Frank Maheshwari, Anil Taylor, Ryan Carleton Univ Sch Comp Sci Ottawa ON K1S 5B6 Canada

ISBN: (纸本)0769526365

We present the first parallel algorithm for building a Hausdorff Voronoi diagram (HVD). Our algorithm is targeted towards cluster computing architectures and computes the Hausdorff Voronoi diagram for non-crossing objects in time O(nlog(4)n/p)for input size n and p processors. In addition, our parallel algorithm also implies a new sequential HVD algorithm that constructs HVDs for noncrossing objects in time O(n log(4) n). this improves on previous sequential results and solves an open problem posed by Papadopoulou and Lee [18].

关键词： parallel algorithms

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A parallel architecture for motion estimation and DCT computation in MPEG-2 encoder

A parallel architecture for motion estimation and DCT comput...

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7th international conference on algorithms and architectures for parallel processing

作者： Huang, Jian Li, Hao Univ North Texas Dept Comp Sci & Engn POB 311366 Denton TX 76203 USA

ISBN: (纸本)9783540729044

this paper presents a parallel architecture that can simultaneously perform block-matching motion estimation (ME) and discrete cosine transform (DCT). Because DCT and ME are both processed block by block, it is preferable to put them in one module for resource sharing. Simulation results performed using Simulink demonstrate that the parallel fashioned architecture improves the performance in terms of running time by 18.6% compared to the conventional sequential fashioned architecture.

关键词： parallel processing systems

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Design Space Explorations for Streaming Accelerators using Streaming Architectural Simulator

Design Space Explorations for Streaming Accelerators using S...

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10th international Bhurban conference on Applied Science and Technology (IBCAST)

作者： Shafiq, Muhammad Peric ' as, Miquel Navarro, Nacho Ayguad'e, Eduard CESAT Islamabad Pakistan

ISBN: (纸本)9781467344265;9781467344258

In the recent years streaming accelerators like GPUs have been pop-up as an effective step towards parallel computing. the wish-list for these devices span from having a support for thousands of small cores to a nature very close to the general purpose computing. this makes the design space very vast for the future accelerators containing thousands of parallel streaming cores. this complicates to exercise a right. choice of the architectural configuration for the next generation devices. However, accurate deign space exploration tools developed for the massively parallel architectures can ease this task. the main objectives of this work are twofold. (i) We present a complete environment of a trace driven simulator named SArcs(1) (Streaming Architectural Simulator) for the streaming accelerators. (ii) We use our simulation tool-chain for the design space explorations of the GPU like streamin g architectures. Our design space explorations for different architectural aspects of a GPU like device are with reference to a base line established for NVIDlA's Fermi architecture (GPU Tesla C2050). the explored aspects include the performance effects by the variations in the configurations of Streamiflg Multiprocessors, Global Memory Bandwidth, Chaflflels between SMs down to Memory Hierarchy and Cache Hierarchy. the explorations are performed using application kernels from m Vector Reduction, 2D-COnvolution, Matrix-Matrix Multiplication and 3D-Stencil. Results show that the configurations of the computational resources for the current Fermi GPU device can deliver higher performance with further improvement in the global memory bandwidth for the same device.

关键词： graphics processing units multiprocessing systems parallel architectures

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