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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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parallel algorithms for Solving Markov Decision Process

引用

9th international conference on algorithms and architectures for parallel processing

作者： Zhang, Qi Sun, Guangzhong Xu, Yinlong Univ Sci & Technol China Dept Comp Sci Hefei 230027 Anhui Peoples R China

ISBN: (纸本)9783642030949

Markov decision process (MDP) provides the foundations for a number of problems, such as artificial intelligence Studying, automated planning and reinforcement learning. MDP can be solved efficiently in theory. However, for large scenarios, more investigations are needed to reveal practical algorithms. algorithms for solving MDP have a natural concurrency. In this paper, we present parallel algorithms based on dynamic programming Meanwhile, the cost of computation and communication complexity of this method is analyzed. Moreover, experimental results demonstrate excellent speedups and scalability.

关键词： Markov Decision Process (MDP) parallel algorithm

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Proceedings of the 10th Annual international Phoenix conference on Computers and Communications

Proceedings of the 10th Annual International Phoenix Confere...

引用

Proceedings of the 10th Annual international Phoenix conference on Computers and Communications

ISBN: (纸本)0818621338

this conference proceedings consists of 121 papers. the following topics are dealt with: real time architectures and applications;neural network implementation and applications;parallelism and computational paradigms of the future;fault tolerance and reliability;performance measurement and evaluation;distributed database systems;parallel and distributed architectures;parallel and distributed algorithms and applications;distributed operating systems;algorithms for distributed operating systems;languages and environments;object-oriented systems;specification methodologies;software engineering;communications theory;recent advances in mobile digital radio;advanced topics in communications systems;digital communications;theory and applications of non-uniform sampling;fiber optics;frame relay networks;network management and standards;protocol design;network performance;local area networks;wide area and broadband networks;multimedia database systems;graphics and multimedia;computer aided design;deductive systems;expert system applications;and AI techniques and expert systems.

关键词： Computer Networks

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Mimer and Schedeval: Tools for Comparing Static Schedulers for Streaming Applications on Manycore architectures 44

Mimer and Schedeval: Tools for Comparing Static Schedulers f...

引用

44th Annual international conference on parallel processing Workshops (ICPPW)

作者： Melot, Nicolas Janzen, Johan Kessler, Christoph Linkoping Univ Linkoping Sweden Uppsala Univ Uppsala Sweden

ISBN: (纸本)9781467375894

Scheduling algorithms published in the scientific literature are often difficult to evaluate or compare due to differences between the experimental evaluations in any two papers on the topic. Very few researchers share the details about the scheduling problem instances they use in their evaluation section, the code that allows them to transform the numbers they collect into the results and graphs they show, nor the raw data produced in their experiments. Also, many scheduling algorithms published are not tested against a real processor architecture to evaluate their efficiency in a realistic setting. In this paper, we describe Mimer, a modular evaluation tool-chain for static schedulers that enables the sharing of evaluation and analysis tools employed to elaborate scheduling papers. We propose Schedeval that integrates into Mimer to evaluate static schedules of streaming applications under throughput constraints on actual target execution platforms. We evaluate the performance of Schedeval at running streaming applications on the Intel Single-Chip Cloud computer (SCC), and we demonstrate the usefulness of our tool-chain to compare existing scheduling algorithms. We conclude that Mimer and Schedeval are useful tools to study static scheduling and to observe the behavior of streaming applications when running on manycore architectures.

关键词： Benchmark testing Energy consumption Processor scheduling Schedules Switches throughput Time-frequency analysis benchmark crown scheduling energy frequency many-core scaling scc scheduling streaming voltage Benchmark testing scheduling of multiprocessor Streaming Time frequency analysis throughput Scheduling algorithms Switches energy consumption BENCHMARKS Stress corrosion cracking Scale formation VOLTAGE Scaling

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Topic 10: parallel Numerical algorithms

引用

18th international conference on Euro-Par parallel processing

作者： Duff, Iain Gallopoulos, Efstratios di Serafino, Daniela Ucar, Bora Top Comm Air Force Base CO 80914 USA

ISBN: (纸本)9783642328206

the solution of large-scale problems in Computational Science and Engineering relies on the availability of accurate, robust and efficient numerical algorithms and software that are able to exploit the power offered by modern computer architectures. Such algorithms and software provide building blocks for prototyping and developing novel applications, and for improving existing ones, by relieving the developers from details concerning numerical methods as well as their implementation in new computing environments.

关键词： Computer architecture

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A proposed asynchronous object load balancing method for parallel 3D image reconstruction applications

A proposed asynchronous object load balancing method for par...

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10th international conference algorithms and architectures for parallel processing, ICA3PP 2010

作者： Alvarez-Bermejo, Jose Antonio Roca-Piera, Javier Dept of Computer Architecture and Electronics Universidad de Almería Ctra. Sacramento S/N. 04120 Spain

ISBN: (纸本)3642131182

Scientific applications usually exhibit irregular patterns of execution and high resource usage. parallel architectures are a feasible solution to face these drawbacks, but porting software to parallel platforms means the addition of an extra layer of complexity to scientific software. Abstractions such as Object Orientation and models like the concurrent object model may be of great help to develop scientific parallel applications. the shared nature of parallel architectures and the stochastic condition of parallel schedulers underline the adaptivity as a desired feature for parallel applications. Load Balancers are key for achieving adaptivity, and benefit from object oriented models in issues like load migration. In this paper we present our experiences when porting scientific software using the concurrent object abstraction and a method to asynchronously invoke load balancers. © Springer-Verlag Berlin Heidelberg 2010.

关键词： parallel architectures

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Evolution of DSP architectures: towards parallelism exploitation

Evolution of DSP architectures: towards parallelism exploita...

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10th Mediterranean Electrotechnical conference (MALECON2000)

作者： Sernec, R. Zajc, M. Tasic, J. IPS Ljubljana Slovenia

this paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and recently adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. the intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallel processing of algorithms.

关键词： Digital signal processing

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Forward Kinematics Development of a 3-RRS parallel Manipulator for Real-Time Control 10

Forward Kinematics Development of a 3-RRS Parallel Manipulat...

引用

10th RSI international conference on Robotics and Mechatronics (ICRoM)

作者： Moosavian, S. Ali A. Mahdizadeh, Omid Hallajian, Sina Ashrafi, Sara Jamali, Mohammad Akbari, Vahid KN Toosi Univ Technol Ctr Excellence Robot & Control Adv Robot & Automated Syst ARAS Lab Dept Mech Engn Tehran Iran

ISBN: (纸本)9781665454520

In control of parallel robots, forward kinematics calculation is mainly required. In some studies, obtained equations are solved numerically with massive calculations that is not acceptable for control implementations. this paper introduces a new method to extract forward kinematics for a 3RRS robot. this method calculates the kinematics of passive joints with two separated equations, which can be solved to decrease the total computation demands. Also, a new weight compensation mechanism is proposed to improve the dynamic response by a linear pneumatic actuator placed between the ground and the end-effector. On the other hand, to use various control algorithms, the position of the rolling ball on the endeffector (moving platform) must be measured. this is performed using Convolutional Neural Networks (CNNs) as image processing algorithms. Since the system must work quickly for a high-frequency task, the proposed image processing algorithm can provide the desired fast feedback. Experimental results reveal the merits of the above-described proposed modules.

关键词： parallel Manipulator Ball & Plate Kinematics Machine Vision Neural Networks

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An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings 30

An efficient compilation of coarse-grained reconfigurable ar...

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30th Euromicro international conference on parallel, Distributed and Network-Based processing (PDP)

作者： Ohwada, Ayaka Kojima, Takuya Amano, Hideharu Keio Univ Yokohama Kanagawa Japan Univ Tokyo Bunkyo Ku Tokyo Japan

ISBN: (纸本)9781665469586

In recent years, IoT devices have become widespread, and energy-efficient coarse-grained reconfigurable architectures (CGRAs) have attracted attention. CGRAs comprise several processing units called processing elements (PEs) arranged in a two-dimensional array. the operations of PEs and the interconnections between them are adaptively changed depending on a target application, and this contributes to a higher energy efficiency compared to general-purpose processors. the application kernel executed on CGRAs is represented as a data flow graph (DFG), and CGRA compilers are responsible for mapping the DFG onto the PE array. thus, mapping algorithms significantly influence the performance and power efficiency of CGRAs as well as the compile lime. this paper proposes POCOCO, a compiler framework for CGRAs that can use pre-optimized subgraph mappings. this contributes to reducing the compiler optimization task. To leverage the subgraph mappings, we extend an existing mapping method based on a genetic algorithm. Experiments on three architectures demonstrated that the proposed method reduces the optimization lime by 48%, on an average, for the best case of the three architectures.

关键词： Program processors throughput Energy efficiency Libraries Reconfigurable architectures Arrays Task analysis

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A Malleable Vectorized Auction Algorithm for Modern Multicore architectures 20

A Malleable Vectorized Auction Algorithm for Modern Multicor...

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20th IEEE international conference on High Performance Computing and Communications (HPCC) / 16th IEEE international conference on Smart City (SmartCity) / 4th IEEE international conference on Data Science and Systems (DSS)

作者： Sena, A. C. Marzulo, L. A. J. Nascimento, A. P. Vasconcelos, C. N. Univ Estado Rio De Janeiro Inst Matemat & Estat Rio De Janeiro Brazil Univ Fed Fluminense Inst Comp Niteroi RJ Brazil

ISBN: (纸本)9781538666142

the auction algorithm has been widely used to solve the bipartite graph matching problem and its parallel implementation is employed to find solutions in a reasonable computational time. Moreover, the new multicore architectures, besides its various cores, have a SIMD instruction set that can increase application performance when exactly the same operations are to be performed on multiple data objects. the aim of this paper is to efficiently execute the auction algorithm on these architectures. To achieve that, a vectorized version was implemented and evaluated. these versions were then run in parallel using the OpenMP library. Finally, to optimize the number of threads used during the execution, a malleable strategy is proposed and evaluated. Results show that the vectorized version outperforms the sequential one by a factor of 10, while the malleable vectorized version was able to adapt its execution to exploit the full potential of multicore architectures.

关键词： Multicore processing Heuristic algorithms Program processors Indexes Bipartite graph conferences

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Multi-target vectorization with MTPS C++ generic library

引用

10th international conference on Applied parallel and Scientific Computing, PARA 2010

作者： Kirschenmann, Wilfried Plagne, Laurent Vialle, Stéphane SINETICS Department EDF R and D France SUPELEC - UMI 2958 France AlGorille INRIA Project Team France

ISBN: (纸本)9783642281440

this article introduces a C++ template library dedicated at vectorizing algorithms for different target architectures: Multi-Target parallel Skeleton (MTPS). Skeletons describing the data structures and algorithms are provided and allow MTPS to generate a code with optimized memory access patterns for the choosen architecture. MTPS currently supports x86-64 multicore CPUs and CUDA enabled GPUs. On these architectures, performances close to hardware limits are observed. © 2012 Springer-Verlag.

关键词： Graphics processing unit

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