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Experiments with a parallel external memory system

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14th international conference on High Performance Computing (HiPC 2007)

作者： Nikseresht, Mohammad R. Hutchinson, David A. Maheshwari, Anil Carleton Univ Sch Comp Sci Ottawa ON K1S 5B6 Canada Carleton Univ Dept Syst & Comp Engn Ottawa ON K1S 5B6 Canada

ISBN: (纸本)9783540772194

the theory of bulk-synchronous parallel computing has produced a large number of attractive algorithms, which are provably optimal in some sense, but typically require that the aggregate random access memory (RAM) of the processors be sufficient to hold the entire data set of the parallel problem instance. In this work we investigate the performance of parallel algorithms for extremely large problem instances relative to the available RAM. We describe a system, parallel External Memory System (PEMS), which allows existing parallel programs designed for a large number of processors without disks to be adapted easily to smaller, realistic numbers of processors, each with its own disk system. Our experiments with PEMS show that this approach is practical and promising and the run times scale predictable with the number of processors and with the problem size.

关键词： parallel processing systems

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XETAL-II: A107 GOPS, 600mW massively-parallel processor for video scene analysis

XETAL-II: A107 GOPS, 600mW massively-parallel processor for ...

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54th IEEE international Solid-State Circuits conference, ISSCC 2007

作者： Abbo, A. Kleihost, R. Choudhary, V. Sevat, L. Wielage, P. Mouy, S. Heijligers, M. Philips Research Laboratories Eindhoven Netherlands NXP Corporate Research Eindhoven Netherlands NXP Semiconductors Eindhoven Netherlands

ISBN: (纸本)1424408539

Xetal-II is a SIMD processor with 320 processing elements delivering a peak performance of 107GOPS on 16b data while dissipating 600mW. A 10Mb on-chip memory can store up to 4 VGA frames allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3Tb/s to sustain the peak-performance. the 74mm2 IC is fabricated in 90nm CMOS. © 2007 IEEE.

关键词： parallel processing systems

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Communication Study and Implementation Analysis of parallel Asynchronous Iterative algorithms on Message Passing architectures

Communication Study and Implementation Analysis of Parallel ...

引用

Euromicro conference on parallel, Distributed and Network-Based processing

作者： D. El Baz LAAS CNRS Toulouse France

the implementation of parallel asynchronous iterative algorithms on message passing architectures is considered. Several issues related to communication via message passing interfaces or libraries such as MPI-1, MPI-2... 详细信息

关键词： Algorithm design and analysis Iterative algorithms Message passing Artificial intelligence Libraries Fault tolerance Grid computing Peer to peer computing Electronic mail Computer science

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Reflective symmetry detection based on parallel projection

Reflective symmetry detection based on parallel projection

引用

8th international conference on Adaptive and Natural Computing algorithms (ICANNGA)

作者： Songi, Ju-Whan Gwun, Ou-Bong Jeonju Univ Sch Liberal Art Jeonju South Korea Chonbuk Natl Univ Div Elect & Informat Engn Jeonju Jeonbuk South Korea

ISBN: (纸本)9783540715900

Reflective symmetry is useful for various areas such as computer vision, medical imaging, and 3D model retrieval system. this paper presents an intuitive reflective symmetry detection method for 3D polygon objects. Without any mapping process the method detects the reflective symmetry plane by parallel projection. this paper defines a continuous measure to estimate how much an object is reflective symmetrical for a projection plane through the center of the object. Also it explores the method to detect the reflective symmetry plane with the measure. the proposed method can detect up to 99% reflective symmetry plane not exceeding 4 degree angle for perfect symmetry objects and detect up to 85% reflective symmetry plane not exceeding 10 degree angle for near symmetry objects using Princeton Shape Benchmark.

关键词： parallel processing systems

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A fully-pipelined parallel architecture for Kalman tracking filter

A fully-pipelined parallel architecture for Kalman tracking ...

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IEEE 18th international conference Application-specific Systems, architectures and Processors, ASAP07

作者： Merhi, Zaher Ghantous, Milad Elgamel, Mohammad Bayoumi, Magdy El-Desouki, Ayman University of Louisiana at Lafayette National Electronic Research Institute

ISBN: (纸本)1424410274

the Kalman filter is a set of mathematical equations that provides an efficient computational (recursive) mean to estimate the state of a process, in a way that minimizes the mean of the squared error. this filter is very powerful in several aspects: it provides estimations of past, present, and future states, and it can do so when the precise nature of the modeled system is unknown, and even with the presence of measurement and process noise. Moreover, Kalman filter for linear estimate is the most complex and precise algorithm used for target tracking. However, using Kaiman filter algorithms in software for multitarget tracking (MTT) radar system would result in a very long computational time which may not be suitable for today's warfare constraints, or real-time processing. Consequently, a hardware alternative has to be developed which may result in big area overhead which is not suitable for today's area constraints such as sensor nodes in a sensor network. In this paper, we break the arrays into their scalar forms, and develop fully-pipelined hardware architecture for the radar tracking Kalman filter, with time division multiplex blocks to decrease the silicon area.. the proposed architecture contains 6 multipliers, 2 dividers, 9 adders, 5 subtractors, one control unit, and some registers and multiplexers for pipeline and control. Simulation results show that the loss in accuracy between the exact track and the estimated is found to be only 4.9% ©2006 IEEE.

关键词： Kalman filters

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Latency hiding in multi-threading and multi-processing of network applications

Latency hiding in multi-threading and multi-processing of ne...

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16th international conference on parallel Architecture and Compilation Techniques, PACT 2007

作者： Guo, Xiaofeng Dai, Jinquan Li, Long Lv, Zhiyuan Chandra, Prashant R. Google Inc. Intel China Software Center Intel Corporation

ISBN: (纸本)0769529445

Network processors employ a multithreaded, chip-multiprocessing architecture to effectively hide memory latency and deliver high performance for packet processing applications. In such a parallel paradigm, when multiple threads modify a shared variable in the external memory, the threads should be properly synchronized such that the accesses to the shared variable are protected by critical sections. therefore, in order to efficiently harness the performance potential of network processors, it is critical to hide the memory latency and synchronization latency in multi-threading and multiprocessing. In this paper, we present a novel program transformation used in the Intel Auto-partitioning C Compiler for IXP, which perform optimal placement of memory access instructions and synchronization instructions for effective latency hiding. Experimental results show that the transformation provides impressive speedup (up-to to 8.5x) and scalability (up-to 72 threads) of the performance for the real-world network application (a 10Gbps Ethernet Core/Metro Router). © 2007 IEEE.

关键词： Synchronization

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Efficient representations of row-sorted 1-variant matrices for parallel string applications

Efficient representations of row-sorted 1-variant matrices f...

引用

7th international conference on algorithms and architectures for parallel processing, ICA3PP 2007

作者： Alves, Carlos Eduardo Rodrigues Cáceres, Edson Norberto Song, Siang Wun Universidade São Judas Tadeu Brazil Universidade Federal de Mato Grosso do Sul Brazil Universidade de São Paulo Brazil

ISBN: (纸本)9783540729044

We investigate the efficient storage of row-sorted 1-variant (m + 1) X (n + 1) matrices, m > n, that have the following properties: the rows are sorted in strictly increasing order and the set of elements of each row differs only by one single element from the set of elements of the next row. It has been shown that row-sorted 1-variant matrices are important in several parallel string comparison applications. Due to the large amount of redundancy in the row elements, we investigate efficient data structures to store such matrices. In this paper we propose a representation that stores a row-sorted 1-variant matrix in O(m log m) space and access time of O(log m) and can be constructed in O(m log m) time. We thus seek a representation that constitutes a nice balance between access time, representation construction time, and space requirement. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Matrix algebra

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MPSoC memory optimization for digital camera applications

MPSoC memory optimization for digital camera applications

引用

Euromicro Symposium on Digital System Design

作者： Y. Bouchebaba B. Lavigueur B. Girodias G. Nicolescu P. G. Paulin STMicroelectronics Italy Ecole Polytechnique de Montrèal Canada

Multiprocessor system-on-a-chip architectures have received a lot of attention in the past years, but few advances in compilation techniques are targeting these architectures. this is particularly true for the exploitation of data locality. Most of the compilation techniques discussed in the literature for parallel architectures are based on single loop nest. However, most multimedia and image processing applications are composed of several loop nests. In this paper, new techniques based on program transformations are proposed to optimize these types of applications. In a monoprocessor architecture, the loop fusion technique is well known. In this paper, the loop fusion is generalized and adapted to a MPSoC architecture. Another technique called "computation propagation " is proposed. It completely removes the temporary arrays and significantly reduces the memory accesses, the memory space and the processing time. Experimental results show that this new technique yields a significant reduction in the number of data cache misses (35%), in processing time (30%) and in channel transactions (85%).

关键词： Digital cameras Multiprocessing systems Image processing Computer architecture Energy consumption parallel architectures Image coding Color Filters Interpolation

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Efficient Mapping and Functional Verification of parallel algorithms on a MultiüContext Reconfigurable Architecture

Efficient Mapping and Functional Verification of Parallel Al...

引用

20th international conference on Architecture of Computing Systems 2007

作者： Markus Rullmann Sebastian Siegel Renate Merker Julio A. Oliveira Filho thomas Schweizer Tobias Oppold Wolfgang Rosenstiel Dresden University of Technology Germany University of Tübingen Germany

parallel multiücontext reconfigurable architectures provide very attractive platforms with respect to computational performance and reconfigurable features. Today's challenge is the exploitation of this reconfigurable and computational potential to ascertain efficient solution for mapping applications onto these architectures. the demand for appropriate tools is evident. In this paper we provide a combination and a mutual adaption of two separate tools to create a continuous design flow for parallel multiücontext reconfigurable architectures. Especially we present the interaction of a parameterized mapping tool for mapping compute intensive algorithms on processor arrays and a subsequent verification of the mapping results using the Configurable Reconfigurable Core (CRC) architecture model. the SystemC implementation of the CRC model leads to a cycle accurate functional simulation of the realization. Using this continuous design flow we derive an efficient realization of the edge detection algorithm (EDA) on a parallel multiücontext reconfigurable architecture. We describe in detail how the parallel realization of the EDA has to be translated in a specification for programming the CRC model.

关键词： Computer architecture Registers parallel processing Partitioning algorithms Computational modeling Context modeling Tiles

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Design and Simulation of parallel algorithms for Motion Estimation

Design and Simulation of Parallel Algorithms for Motion Esti...

引用

international conference on Information Technology (ICIT)

作者： Debapriya Bhattacharyya Amlan Chakrabarti Shamik Misra A.K.Choudhury School of Information Technology University of Calcutta Kolkata West Bengal India School of Information Technology West Bengal University of Technology Kolkata West Bengal India

Block-based motion estimation technique is being widely used in video compression applications, for the removal of video temporal redundancy. In this paper we have implemented the six-level nested do-loop full-search block-matching motion estimation algorithm proposed by *** and *** by breaking the respective frames into macroblocks. We have used Matlab for the simulation of the algorithm and the results obtained is being presented in this paper. We have first implemented the algorithm using 25 movie frames without breaking them into macroblocks, in the next phase we have implemented the same after breaking the frames into the respective macroblocks. We have also proposed a multi processing based architecture for the hardware implementation of the simulated algorithm.

关键词： Algorithm design and analysis parallel algorithms Motion estimation Video compression Information technology Layout Video sequences Decoding Image reconstruction Robots

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