检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,694 篇 会议
58 册 图书
53 篇 期刊文献

馆藏范围

2,805 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,844 篇 工学
- 1,629 篇 计算机科学与技术...
- 847 篇 软件工程
- 340 篇 电气工程
- 222 篇 电子科学与技术（可...
- 209 篇 信息与通信工程
- 84 篇 控制科学与工程
- 63 篇 光学工程
- 57 篇 机械工程
- 41 篇 仪器科学与技术
- 39 篇 生物医学工程（可授...
- 38 篇 生物工程
- 31 篇 材料科学与工程（可...
- 25 篇 动力工程及工程热...
- 21 篇 化学工程与技术
- 20 篇 建筑学
- 15 篇 土木工程
- 13 篇 力学（可授工学、理...
- 12 篇 交通运输工程
499 篇 理学
- 343 篇 数学
- 113 篇 物理学
- 51 篇 系统科学
- 48 篇 生物学
- 30 篇 统计学（可授理学、...
- 26 篇 化学
173 篇 管理学
- 119 篇 管理科学与工程(可...
- 62 篇 图书情报与档案管...
- 49 篇 工商管理
40 篇 医学
- 30 篇 临床医学
- 14 篇 基础医学(可授医学...
15 篇 法学
- 15 篇 社会学
9 篇 经济学
9 篇 农学
8 篇 文学
2 篇 军事学
1 篇 教育学

主题

363 篇 parallel process...
219 篇 computer archite...
205 篇 graphics process...
146 篇 parallel archite...
136 篇 graphics process...
129 篇 hardware
116 篇 parallel algorit...
112 篇 image processing
99 篇 computational mo...
94 篇 concurrent compu...
87 篇 instruction sets
86 篇 field programmab...
83 篇 algorithm design...
79 篇 multicore proces...
77 篇 signal processin...
76 篇 parallel process...
66 篇 parallel program...
60 篇 throughput
60 篇 gpu
59 篇 kernel

机构

11 篇 natl univ def te...
6 篇 college of compu...
6 篇 school of comput...
6 篇 hosei univ dept ...
6 篇 natl univ def te...
5 篇 univ aizu dept c...
5 篇 carleton univ sc...
5 篇 school of comput...
5 篇 computer science...
5 篇 inria rennes
5 篇 city university ...
4 篇 chinese acad sci...
4 篇 univ michigan ad...
4 篇 institute of com...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 univ jaume 1 dep...
4 篇 hainan internati...
4 篇 tech univ cluj n...
4 篇 department of co...

作者

11 篇 jack dongarra
10 篇 roman wyrzykowsk...
9 篇 konrad karczewsk...
9 篇 quintana-orti en...
7 篇 dongarra jack
7 篇 kothapalli kisho...
6 篇 hannig frank
6 篇 liu jie
6 篇 su jinshu
6 篇 nakano koji
6 篇 peng shietung
6 篇 li yamin
6 篇 chu wanming
6 篇 wyrzykowski roma...
6 篇 thulasiraman par...
5 篇 ito yasuaki
5 篇 jerzy waśniewski
5 篇 wang guojun
5 篇 geyong min
5 篇 wanlei zhou

语言

2,744 篇 英文
36 篇 其他
18 篇 中文
11 篇 俄文
2 篇 乌克兰文
1 篇 西班牙文

检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2805 条记录，以下是2141-2150 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Real-time nonlinear finite element analysis for surgical simulation using graphics processing units

Real-time nonlinear finite element analysis for surgical sim...

引用

10th international conference on Medical Image Computing and Computer-Assisted Intervention (MICCAI 2007)

作者： Taylor, Zeike A. Cheng, Mario Ourselin, Sebastien CSIRO ICT Ctr e Hlth Res Ctr BioMedIA Lab Level 20300 Adelaide St Brisbane Qld 4000 Australia UCL Ctr Med Image Comp London WC1E 6BT England

ISBN: (纸本)9783540757566

Clinical employment of biomechanical modelling techniques in areas of medical image analysis and surgical simulation is often hindered by conflicting requirements for high fidelity in the modelling approach and high solution speeds. We report the development of techniques for high-speed nonlinear finite element (FE) analysis for surgical simulation. We employ a previously developed nonlinear total Lagrangian explicit FE formulation which offers significant computational advantages for soft tissue simulation. However, the key contribution of the work is the presentation of a fast graphics processing unit (CPU) solution scheme for the FE equations. To the best of our knowledge this represents the first CPU implementation of a nonlinear FE solver. We show that the present explicit FE scheme is well-suited to solution via highly parallel graphics hardware, and that even a midrange GPU allows significant solution speed gains (up to 16.4x) compared with equivalent CPU implementations. For the models tested the scheme allows realtime solution of models with up to 16000 tetrahedral elements. the use of GPUs for such purposes offers a cost-effective high-performance alternative to expensive multi-CPU machines, and may have important applications in medical image analysis and surgical simulation.

关键词： Image processing

来源：评论

学校读者我要写书评

暂无评论

Low-Complexity architectures of a Decoder for IEEE 802.16e LDPC Codes

Low-Complexity Architectures of a Decoder for IEEE 802.16e L...

引用

Euromicro Symposium on Digital System Design

作者： Giuseppe Gentile Massimo Rovini Luca Fanucci Department of Information Engineering University of Pisa Pisa Italy

Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. this paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. the decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with serial processing units working in pipeline to reduce the latency. Particularly, two different architectures are considered, and their RTL/memory complexity tradeoffs are analyzed. the resulting design yields a throughput ranging from 93 to 497 Mbps by means of 15 iterations at the clock frequency of 400 MHz. Synthesis on 65 nm CMOS technology, shows a chip area less than 0.59 mm 2 , despite the high flexibility, which compares favourably with similar implementations.

关键词： Decoding Parity check codes CMOS technology Error correction codes Wireless LAN Metropolitan area networks Code standards Convergence Pipelines Delay

来源：评论

学校读者我要写书评

暂无评论

parallel Mining of Frequent Closed Patterns: Harnessing Modern Computer architectures

Parallel Mining of Frequent Closed Patterns: Harnessing Mode...

引用

7th IEEE international conference on Data Mining (ICDM 2007)

作者： Claudio Lucchese Salvatore Orlando Raffaele Perego Ca Foscari University Venice Italy National Research Council Pisa Italy

Inspired by emerging multi-core computer architectures, in this paper we present ***, a multi-threaded algorithm for frequent closed itemset mining (FCIM). To the best of our knowledge, this is the first FCIM parallel algorithm proposed so far. We studied how different duplicate checking techniques, typical of FCIM algorithms, may affect this parallelization. We showed that only one of them allows to decompose the global FCIM problem into independent tasks that can be executed in any order, and thus in parallel. Finally we show how MT-CLOSED efficiently harness modern CPUs. We designed and tested several parallelization paradigms by investigating static/dynamic decomposition and scheduling of tasks, thus showing its scalability w.r.t. to the number of CPUs. We analyzed the cache friendliness of the algorithm. Finally, we provided additional speed-up by introducing SIMD extensions.

关键词： Computer architecture Data mining Algorithm design and analysis Itemsets Dynamic scheduling Yarn parallel algorithms parallel processing Coprocessors Data structures

来源：评论

学校读者我要写书评

暂无评论

Energy Based Design Space Exploration of Multiprocessor VLIW architectures

Energy Based Design Space Exploration of Multiprocessor VLIW...

引用

Euromicro Symposium on Digital System Design

作者： Manoj Gupta Mayank Gupta Neeraj Goel M. Balaksrishnan Departament d’ Arquitectura de Computadors Universitat Politècnica de Catalunya Veveo Inc. Department of Computer Science & Engineering Indian Institute of Technology Delhi

Today energy is an important factor in designing a multiprocessor system. the overall goal of this work is to propose a methodology for design space exploration of VLIW multiprocessors. We have developed a framework which enables us to explore energy - performance trade-off for state of the art VLIW processors and multiprocessors. Our methodology is capable of simultaneously exploring process-processor binding while tuning the individual VLIW processors to support specific operation concurrency requirements of processes bound to it. We extend existing uniprocessor instruction level energy estimation techniques to multiprocessors. the implementation is based on popular public domain tools like IMPACT and SystemC. Its completeness, robustness and efficacy is demonstrated through a case study on MPEG-2 decoder.

关键词： Space exploration VLIW parallel processing Decoding Registers Application software Computer architecture Multiprocessing systems Concurrent computing Instruction sets

来源：评论

学校读者我要写书评

暂无评论

A Lightweight Model for Software thread-Level Speculation (TLS) 07

A Lightweight Model for Software Thread-Level Speculation (T...

引用

international conference on parallel Architecture and Compilation Techniques (PACT)

作者： Cosmin E. Oancea Alan Mycroft Computer Laboratory University of Cambridge Cambridge UK

ISBN: (纸本)9780769529448

Rundberg and StenstrÖm introduced one of the first models for software TLS. this increases the loop parallelism by speculatively executing iterations while keeping a log of reads and writes; if a conflict occurs then mis-speculated iterations are re-executed (rollback). this is useful for code falling outside the traditional static dependence analysis framework. their technique simulates cache-coherency hardware and is exact in that rollback only takes place when a dependence violation occurs, but the coherency overheads are too large for general practical use. Our contribution is a family of abstract coherency algorithms; while being safe (detect all violations), these trade false positives (which cause unnecessary rollbacks) against coherency algorithm space and time. this paper gives one such algorithm.

关键词： Yarn parallel architectures Concurrent computing Laboratories parallel processing Hardware Runtime

来源：评论

学校读者我要写书评

暂无评论

Exploiting parallelism in Double Path Adders' Structure for Increased throughput of Floating Point Addition

Exploiting Parallelism in Double Path Adders' Structure for ...

引用

Euromicro Symposium on Digital System Design

作者： Alexandru Amaricai Mircea Vladupiu Lucian Prodan Mihai Udrescu Oana Boncalo Computer Science and Engineering Department “Politehnica” University of Timisoara Romania Computer Science and Engineering Department “Politehnica” University of Timisoara

this paper proposes a novel approach for increasing the performance of the floating point addition, by efficiently exploiting both paths from the classical double path adder. thus, it becomes possible to execute two floating point additions simultaneously using a single adder, each on a different path. Performing two floating point additions in this manner will requires duplication of the signs and exponent computation modules. the cost estimates show a 20% increase of the active area for the proposed adder compared with other floating point adders. In terms of performance, the latency of the proposed adder is slightly higher with respect to other double path adders. However, the increased latency is compensated by the increased throughput obtained.

关键词： throughput Adders Delay Circuits parallel processing Costs Concurrent computing Computer architecture Computer science Design optimization

来源：评论

学校读者我要写书评

暂无评论

Hardware acceleration for sparse fourier image reconstruction

Hardware acceleration for sparse fourier image reconstructio...

引用

international conference on ASIC

作者： Quang Dinh Yoram Bresler Demmg Chen Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign USA

Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with fie Id-program m able gate arrays (FPGAs). the FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. the design is estimated to provide even more speedup on a next-generation RC platform.

关键词： Hardware Acceleration Image reconstruction Field programmable gate arrays Iterative algorithms Supercomputers Computer architecture Biomedical imaging parallel processing Fabrics

来源：评论

学校读者我要写书评

暂无评论

Dynamic SMP Clusters with Communication on the Fly in SoC Technology Applied for Medium-Grain parallel Matrix Multiplication

Dynamic SMP Clusters with Communication on the Fly in SoC Te...

引用

Euromicro conference on parallel, Distributed and Network-Based processing

作者： M. Tudruj L. Masko Polish Japanese Institute of Information Technology Warsaw Poland Institute of Computer Science Polish Academy of Sciences Warsaw Poland

the paper presents a study of medium and coarse grain numerical computations in a new cluster-based shared memory parallel architecture oriented into implementation in "Systems on Chip" (SoC) technology. the assumed architecture is based on dynamic processor clusters, organized around shared memory modules. Fast shared data transfers between processors from different clusters are performed through communication on the fly, which is a synergy of processor switching between clusters and intra-cluster data reads on the fly. Dynamic processor clusters are implemented inside SoC modules additionally connected by a global inter-cluster network. the paper discusses speedup and parallelization efficiency of parallel matrix multiplication estimated by symbolic execution of program graphs. Simulation results are presented for algorithms with two kinds of data decomposition: recursive division of matrices into quadrants and division of matrices into stripes. In the quadrant-based method, elementary square sub-matrix multiplications are performed using the serial Strassen method and the communication on the fly is applied. the experiments reveal much higher efficiency of the proposed quadrant-based matrix multiplication method than that of the "stripe" method, considered very efficient in conventional parallel shared memory systems

关键词： Concurrent computing Computer architecture Matrix decomposition Communication switching System-on-a-chip Computational modeling Data communication Embedded computing parallel architectures Global communication

来源：评论

学校读者我要写书评

暂无评论

Latency Hiding in Multi-threading and Multi-processing of Network Applications 07

Latency Hiding in Multi-Threading and Multi-Processing of Ne...

引用

international conference on parallel Architecture and Compilation Techniques (PACT)

作者： Xiaofeng Guo Jinquan Dai Long Li Zhiyuan Lv Prashant R. Chandra Google Inc. USA Intel China Software Center China Intel Corporation USA

ISBN: (纸本)9780769529448

Network processors employ a multithreaded, chip-multiprocessing architecture to effectively hide memory latency and deliver high performance for packet processing applications. In such a parallel paradigm, when multiple threads modify a shared variable in the external memory, the threads should be properly synchronized such that the accesses to the shared variable are protected by critical sections. therefore, in order to efficiently harness the performance potential of network processors, it is critical to hide the memory latency and synchronization latency in multi-threading and multiprocessing. In this paper, we present a novel program transformation used in the Intelreg Auto-partitioning C Compiler for IXP, which perform optimal placement of memory access instructions and synchronization instructions for effective latency hiding. Experimental results show that the transformation provides impressive speedup (up-to to 8.5x) and scalability (up- to 72 threads) of the performance for the real-world network application (a 10Gbps Ethernet Core/Metro Router).

关键词： Delay Program processors Yarn Application software Random access memory Protection Scalability Optimizing compilers parallel architectures Programming

来源：评论

学校读者我要写书评

暂无评论

A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier

A VLSI architecture for a Run-time Multi-precision Reconfigu...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Zhou Shun Oliver A. Pfander Hans-Jorg Pfleiderer Amine Bermak Electrical and Computer Engineering Department Hong Kong University of Science and Technology Hong Kong China Institute for Microelectronics University of Ulm (EBS) Germany

In this paper, a reconflgurable multi-precision Radix-4 Booth multiplier structure is presented. the reconfig- urable 8 x 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. the number of bits can be extended by concatenating more stages together. For example, four 8 x8 bit units can be used to build a 16 x 16 bit Booth multiplier. In our proposed architecture, the multiplier adapts to different bit-lengths by using external control signals. the performance of our reconflgurable multiplier are compared with a parallel array multiplier and a conventional Booth multiplier. the comparison is based on synthesis results obtained by synthesizing all multiplier architectures targeting a Xilinx FPGA. the overhead resulting from our reconfiguration scheme are also evaluated and compared to a conventional Booth and array multipliers.

关键词： Very large scale integration Runtime Signal processing algorithms Energy consumption Field programmable gate arrays Delay Signal synthesis Digital signal processing Silicon Computer architecture

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共281页 << < 211 212 213 214 215 216 217 218 219 220 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：