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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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the UCSC Kestrel Application-Unspecific Processor

The UCSC Kestrel Application-Unspecific Processor

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Richard Hughey Andrea Di Blas Department of Computer Engineering University of California Santa Cruz CA USA University of California Santa Cruz Santa Cruz CA US

the UCSC Kestrel parallel processor is part of an evolution from application-specific to specialized to application-unspecific processing. Kestrel combines an ALU, multiplier, and local memory, with systolic shared registers for seamless merging of communication and computation, and an innovative condition stack for rapid conditionals. the result has been a readily programmable and efficient co-processor for many applications. Experience with Kestrel indicates that programmable systolic processing, and its natural combination with the single instruction-multiple data (SIMD) parallel architecture, will be an effective design choice for years to come

关键词： Signal processing algorithms Sequences Costs Very large scale integration Systolic arrays Registers Bioinformatics Biology computing Algorithm design and analysis Concurrent computing

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Configurable Computing Platforms - Promises, Promises

Configurable Computing Platforms - Promises, Promises

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Carl Ebeling Department of Computer Science and Engineering University of Washington USA

For some time now, configurable computing has been hailed as the future for application-specific architectures. the purported advantages are well-known: the increasing NRE cost of chip fab is avoided, the same platform can be used for a variety of applications, and implementations can be fixed or upgraded in the field. But in spite of many attempts to move configurable computing platforms into the mainstream, they have yet to achieve their full promise. this talk will explore the barriers that have kept configurable computing on the sidelines thus far, and suggest steps that we might take to take advantage of its full potential

关键词： Field programmable gate arrays Hardware Computer architecture Costs Signal processing algorithms Embedded computing parallel processing Programming profession Computer science Application software

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Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy

Minimum Cost for Channels and Registers in Processor Arrays ...

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Sebastian Siegel Renate Merker Institute of Circuits and Systems Dresden University of Technology Dresden Germany

In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algorithmic data dependencies within the processor array (PA) with minimum cost for channels and registers. there, we use a new mapping approach which allows a direct mapping of the algorithm onto the PA by a partitioning method. In contrast to existing approaches, we consider the issue of avoiding redundant usage of channels and registers, which can appear if one instance of a variable has to be transferred from a source PE to several sink PEs. Further, a solution of the optimization problem determines the schedule for the transfer of the variable instances in the channels and their storage in registers as well as the inner schedule for the operations in the PEs. We illustrate our method on the edge detection algorithm.

关键词： Registers Partitioning algorithms Difference equations Cost function Image edge detection parallel processing Algorithm design and analysis Circuits and systems Acceleration Topology

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Low Complexity Design of High Speed parallel Decision Feedback Equalizers

Low Complexity Design of High Speed Parallel Decision Feedba...

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Daesun Oh Keshab K. Parhi Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA

this paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. the novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.

关键词： Decision feedback equalizers Multiplexing Hardware Feedback loop Intersymbol interference Pipeline processing Magnetic recording throughput Computer architecture Upper bound

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A Task Balancing and Collaborative Strategy for View Maintenance Based on CSCW

A Task Balancing and Collaborative Strategy for View Mainten...

引用

international conference on Computer Supported Cooperative Work in Design

作者： Yayao Zuo Yong Tang Zhongmei Shu Faculty of Computer Guangdong University of Technology Guangzhou China Department of Computer Science Sun Yat-sen University Guangzhou China

ISBN: (纸本)142440164X

Materialized view (MV) maintenance is an important research area in the database and data warehouse area. Currently, most of the MV maintenance methods are based on the C/S or B/S model, and the MV tasks are recomputed sequentially, which cause the system to overload and even crash. To address the problem, decomposition of the maintenance task is explored based on task balancing collaborative strategy, which is also applicable to the CSCW systems for managing, searching and processing data

关键词： Data warehouses Collaborative work Computer crashes international collaboration Sun Computational Intelligence Society Database systems Load management Scalability parallel processing

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Priority Based Scheduling for Heterogeneous Grid Environments

Priority Based Scheduling for Heterogeneous Grid Environment...

引用

international conference on Communication Systems

作者： G. Sumathi N. P. Gopalan Department of Information Technology Sri Venkateswara College of Engineering Sirperumbudur India Department of Computer Applications National Institute of Technology Tiruchirappalli India

Grids have emerged as paradigms for the next generation parallel and distributed computing. Computational grid can be defined as large-scale high-performance distributed computing environments that provide access to high-end computational resources. Grid scheduling is the process of scheduling jobs over grid resources. Improving overall system performance with a lower turn around time is an important objective of grid scheduling. In this paper a priority based scheduling algorithm is proposed. In this algorithm a new parameter named "priority" has been taken into consideration. the algorithm classifies the jobs into high, medium and low categories based on their priority. the priority assignment is done by considering the computational power of job and level of parallelism. the value for level of parallelism is assigned based on the amount of parallelism exhibited by the job and the amount of parallelism exhibited by the available resources. Generally, a job, which needs high computational power and exhibits low parallelism is given a high priority. Prioritizing the jobs in this way can improve the performance of computational grids. the effectiveness of our algorithm is evaluated through simulation results and its superiority over other known algorithms is demonstrated

关键词： Processor scheduling Grid computing Distributed computing Scheduling algorithm parallel processing Geographic Information Systems Resource management Large-scale systems System performance Concurrent computing

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Distributed and parallel Computing - 6th international conference on algorithms and architectures for parallel processing, ICA3PP, Proceedings

引用

6th international conference on algorithms and architectures for parallel processing, ICA3PP

ISBN: (纸本)3540292357

the proceedings contain 52 papers. the topics discussed include: improving concurrent write scheme in file server group;a practical comparison of cluster operating systems implementing sequential and transactional consistency;a recursive-adjustment co-allocation scheme in data grid environments;reducing the bandwidth requirements of P2P keyword indexing;localization techniques for cluster-based data grid;an efficient dynamic load-balancing algorithm in a large scale cluster;job scheduling policy for high throughput grid computing;data distribution strategies for domain decomposition applications in grid environments;and a practical comparison of cluster operating systems implementing sequential and transactional consistency.

关键词： Distributed computer systems

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2D-VLIW: An Architecture Based on the Geometry of Computation

2D-VLIW: An Architecture Based on the Geometry of Computatio...

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Ricardo Santos Rodolfo Azevedo Guido Araujo Institute of Computing State University of Campinas Sao Paulo Brazil

this work proposes a new architecture and execution model called 2D-VLIW. this architecture adopts an execution model based on large pieces of computation running over a matrix of functional units connected by a set of local register spread across the matrix. Experiments using the Mediabench and SPECint00 programs and the Trimaran compiler show performance gains ranging from 5% to 63%, when comparing the proposal to an EPIC architecture with the same number of registers and functional units. It also show that the g72-enc program running on a 2D-VLIW3times3 matrix had a speedup of 1.37 over a 2times2 matrix while the same program over the EPIC processor with 9 functional units had a speedup of 1.12 over an EPIC processor with 4 functional units. For some internal procedures from Mediabench and SPECint programs, the average 2D-VLIW OPC (operations per cycle) was up to 10 times greater than for the equivalent EPIC processor

关键词： Computer architecture Computational geometry parallel processing VLIW Hardware Registers Performance gain Pipelines Solid modeling Program processors

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parallel numerical solution to large-scale eigenvalue problem in master equation of protein folding kinetics

Parallel numerical solution to large-scale eigenvalue proble...

引用

international conference on Advanced Information Networking and Applications (AINA)

作者： Yiming Li Shao-Ming Yu Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan Department of Computer Science National Chiao Tung University Hsinchu Taiwan

A master equation characterizes the time-evolution of trajectories, the transition of states in protein folding kinetics. Numerical solution of the master equation requires calculating eigenvalues for the corresponding large scale eigenvalue problem. In this paper, we present a parallel computing technique to compute the eigenvalues of the matrix with an N-dimensional vector of the instantaneous probability of the N conformations. parallelization of the implicitly restarted Arnoldi method is successfully implemented on a PC-based Linux cluster. the parallelization scheme used in this work mainly partitions the operations of the matrix. For the Arnoldi factorization, we replicate the upper Hessenberg matrix H/sub m/ for each processor, and distribute the set of Arnoldi vectors V/sub m/ among processors. Each processor performs its own operations. this algorithm is implemented on a PC-based Linux cluster with message passing interface (MPI) libraries. Our preliminary numerical experiment performing on the 32-nodes PC-based Linux cluster has shown that the maximum difference among CPUs is within 10%. A 23 times speedup and 72% parallel efficiency are also attained for the tested cases. this approach enables us to explore large scale dynamics of protein folding.

关键词： Large-scale systems Eigenvalues and eigenfunctions Equations Proteins Kinetic theory Linux parallel processing Concurrent computing Clustering algorithms Partitioning algorithms

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On Cache Contention of parallel Protocol processing in SMT

On Cache Contention of Parallel Protocol Processing in SMT

引用

2006 10th international conference on Communication Technology（ICCT 2006）

作者： Zhibin Zhang Institute of Computing Technology, Chinese Academy of Sciences Graduate University of Chinese Academy of Science Beijing, China Li Guo Institute of Computing Technology, Chinese Academy of Sciences Beijing, China

High performance protocol processing plays more and more important role in current high speed network security. Recent studies show that current computer architecture advances and CPU performance improvement has limited impact on network protocol processing performance. Some researchers find that on real SMT processor like Intel Xeon processor with Hyper-threadings, the sharing resources (like cache) contention between threads can hurt the performance of network processing applications like servers or IDS. In this paper, we put our focus on the processing performance of TCP automata phases, using execution based simulations to model the relation between each phase cache behavior and cache size, and then measuring the cache contention between threads

关键词： Intel On Cache Contention of parallel Protocol processing in SMT Cache Protocol

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