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international conference on Communication Systems

作者： G. Sumathi N. P. Gopalan Department of Information Technology Sri Venkateswara College of Engineering Sirperumbudur India Department of Computer Applications National Institute of Technology Tiruchirappalli India

Grids have emerged as paradigms for the next generation parallel and distributed computing. Computational grid can be defined as large-scale high-performance distributed computing environments that provide access to high-end computational resources. Grid scheduling is the process of scheduling jobs over grid resources. Improving overall system performance with a lower turn around time is an important objective of grid scheduling. In this paper a priority based scheduling algorithm is proposed. In this algorithm a new parameter named "priority" has been taken into consideration. the algorithm classifies the jobs into high, medium and low categories based on their priority. the priority assignment is done by considering the computational power of job and level of parallelism. the value for level of parallelism is assigned based on the amount of parallelism exhibited by the job and the amount of parallelism exhibited by the available resources. Generally, a job, which needs high computational power and exhibits low parallelism is given a high priority. Prioritizing the jobs in this way can improve the performance of computational grids. the effectiveness of our algorithm is evaluated through simulation results and its superiority over other known algorithms is demonstrated

关键词： Processor scheduling Grid computing Distributed computing Scheduling algorithm parallel processing Geographic Information Systems Resource management Large-scale systems System performance Concurrent computing

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Distributed and parallel Computing - 6th international conference on algorithms and architectures for parallel processing, ICA3PP, Proceedings

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6th international conference on algorithms and architectures for parallel processing, ICA3PP

ISBN: (纸本)3540292357

the proceedings contain 52 papers. the topics discussed include: improving concurrent write scheme in file server group;a practical comparison of cluster operating systems implementing sequential and transactional consistency;a recursive-adjustment co-allocation scheme in data grid environments;reducing the bandwidth requirements of P2P keyword indexing;localization techniques for cluster-based data grid;an efficient dynamic load-balancing algorithm in a large scale cluster;job scheduling policy for high throughput grid computing;data distribution strategies for domain decomposition applications in grid environments;and a practical comparison of cluster operating systems implementing sequential and transactional consistency.

关键词： Distributed computer systems

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2D-VLIW: An Architecture Based on the Geometry of Computation

2D-VLIW: An Architecture Based on the Geometry of Computatio...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Ricardo Santos Rodolfo Azevedo Guido Araujo Institute of Computing State University of Campinas Sao Paulo Brazil

this work proposes a new architecture and execution model called 2D-VLIW. this architecture adopts an execution model based on large pieces of computation running over a matrix of functional units connected by a set of local register spread across the matrix. Experiments using the Mediabench and SPECint00 programs and the Trimaran compiler show performance gains ranging from 5% to 63%, when comparing the proposal to an EPIC architecture with the same number of registers and functional units. It also show that the g72-enc program running on a 2D-VLIW3times3 matrix had a speedup of 1.37 over a 2times2 matrix while the same program over the EPIC processor with 9 functional units had a speedup of 1.12 over an EPIC processor with 4 functional units. For some internal procedures from Mediabench and SPECint programs, the average 2D-VLIW OPC (operations per cycle) was up to 10 times greater than for the equivalent EPIC processor

关键词： Computer architecture Computational geometry parallel processing VLIW Hardware Registers Performance gain Pipelines Solid modeling Program processors

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parallel numerical solution to large-scale eigenvalue problem in master equation of protein folding kinetics

Parallel numerical solution to large-scale eigenvalue proble...

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international conference on Advanced Information Networking and Applications (AINA)

作者： Yiming Li Shao-Ming Yu Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan Department of Computer Science National Chiao Tung University Hsinchu Taiwan

A master equation characterizes the time-evolution of trajectories, the transition of states in protein folding kinetics. Numerical solution of the master equation requires calculating eigenvalues for the corresponding large scale eigenvalue problem. In this paper, we present a parallel computing technique to compute the eigenvalues of the matrix with an N-dimensional vector of the instantaneous probability of the N conformations. parallelization of the implicitly restarted Arnoldi method is successfully implemented on a PC-based Linux cluster. the parallelization scheme used in this work mainly partitions the operations of the matrix. For the Arnoldi factorization, we replicate the upper Hessenberg matrix H/sub m/ for each processor, and distribute the set of Arnoldi vectors V/sub m/ among processors. Each processor performs its own operations. this algorithm is implemented on a PC-based Linux cluster with message passing interface (MPI) libraries. Our preliminary numerical experiment performing on the 32-nodes PC-based Linux cluster has shown that the maximum difference among CPUs is within 10%. A 23 times speedup and 72% parallel efficiency are also attained for the tested cases. this approach enables us to explore large scale dynamics of protein folding.

关键词： Large-scale systems Eigenvalues and eigenfunctions Equations Proteins Kinetic theory Linux parallel processing Concurrent computing Clustering algorithms Partitioning algorithms

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On Cache Contention of parallel Protocol processing in SMT

On Cache Contention of Parallel Protocol Processing in SMT

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2006 10th international conference on Communication Technology（ICCT 2006）

作者： Zhibin Zhang Institute of Computing Technology, Chinese Academy of Sciences Graduate University of Chinese Academy of Science Beijing, China Li Guo Institute of Computing Technology, Chinese Academy of Sciences Beijing, China

High performance protocol processing plays more and more important role in current high speed network security. Recent studies show that current computer architecture advances and CPU performance improvement has limited impact on network protocol processing performance. Some researchers find that on real SMT processor like Intel Xeon processor with Hyper-threadings, the sharing resources (like cache) contention between threads can hurt the performance of network processing applications like servers or IDS. In this paper, we put our focus on the processing performance of TCP automata phases, using execution based simulations to model the relation between each phase cache behavior and cache size, and then measuring the cache contention between threads

关键词： Intel On Cache Contention of parallel Protocol processing in SMT Cache Protocol

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FPGA accelerated tate pairing based cryptosystems over binary fields

FPGA accelerated tate pairing based cryptosystems over binar...

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IEEE international conference on Field-Programmable Technology (FPT)

作者： Chang Shu Soonhak Kwon Kris Gaj Department of Electrical & Computer Engineering George Mason University Fairfax VA USA Department of Mathematics Sungkyunkwan University Suwon South Korea

Tate pairing based cryptosystems have recently emerged as an alternative to traditional public key cryptosystems because of their ability to be used in multi-party identity-based key management schemes. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. three schemes for Tate pairing computations have been proposed in the literature: cubic elliptic, binary elliptic, and binary hyperelliptic. For our implementation we have chosen the binary elliptic case because of the simple underlying algorithms and efficient binary arithmetic. In this paper, we propose a new FPGA-based architecture of the Tate pairing-based computation over the binary fields F 2239 and F 2283 . Even though our field sizes are larger than in the architectures based on cubic elliptic curves or binary hyperelliptic curves with the same security strength, nevertheless fewer multiplications in the underlying field need to performed. As a result, the computational latency for a pairing computation has been reduced, and our implementation runs 10-to-20 times faster than the equivalent implementations of other pairing-based schemes at the same level of security strength. At the same time, an improvement in the product of latency by area by a factor between 12 and 46 for an equivalent type of implementation has been achieved

关键词： Field programmable gate arrays Acceleration Public key cryptography Identity-based encryption Elliptic curve cryptography Computer architecture Security Delay Identity management systems parallel processing

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Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors

Integrating Compiler and System Toolkit Flow for Embedded VL...

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IEEE international conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Chi Wu Kun-Yuan Hsieh Yung-Chia Lin Chung-Ju Wu Wen-Li Shih S. C. Chen Chung-Kai Chen Chien-Ching Huang Yi-Ping You Jenq Kuen Lee Department of Computer Science National Tsing-Hua University Hsinchu Taiwan

To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable-length encodings for instructions, and special data paths are frequently adopted. this creates challenges to deploy software toolkits for new embedded DSP processors. this article presents our methods and experiences to develop software and toolkit flows for PAC (parallel architecture core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger and DSP micro-kernels. We first retarget open research compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assembler are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dual-core environments. the footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations

关键词： VLIW Digital signal processing Registers Encoding Software tools Assembly Application software Embedded software parallel architectures Pipelines

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Chaotic Pseudorandom Bit Generator Using n-dimensional Nonlinear Digital Filter

Chaotic Pseudorandom Bit Generator Using n-dimensional Nonli...

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2006 10th international conference on Communication Technology（ICCT 2006）

作者： Xiaomin Wang1, Jiashu Zhang1, Yongquan Fan1,Wenfang Zhang2 1Key Lab of Signal and Information processing, Southwest Jiaotong University, Chengdu,610031, P.R. China 2Key Lab of Network Security and National Computing Grid, Southwest Jiaotong University, Chengdu, Sichuan, China

A chaotic pseudorandom bit generator (PRBG) using n-dimensional NDF is proposed. To overcome the effects of finite wordlength to NDF and to hide its dynamic behavior, a coupling method followed by a quantization function is adopted. Detailed theoretical analyses show that the proposed PRBG has perfect cryptographic properties, and can be used to construct stream ciphers with higher security than other chaotic ciphers. Moreover, it is much faster than other chaotic pseudo random number generators due to the inherent parallel structure of NDF. Finally, some experiments are made for confirmation.

关键词： NDF Chaotic Pseudorandom Bit Generator Using n-dimensional Nonlinear Digital Filter

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Automatic tuning matrix multiplication performance on graphics hardware 05

Automatic tuning matrix multiplication performance on graphi...

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14th international conference on parallel architectures and Compilation Techniques

作者： Jiang, CH Snir, M Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)076952429X

In order to utilize the tremendous computing power of graphics hardware and to automatically adapt to the fast and frequent changes in its architecture and performance characteristics, this paper implements an automatic tuning system to generate high-performance matrix-multiplication implementation on graphics hardware. the automatic tuning system uses a parameterized code generator to generate multiple versions of matrix multiplication, whose performances are empirically evaluated by actual execution on the target platform. An ad-hoc search engine is employed to search over the implementation space for the version that yields the best performance. In contrast to similar systems on CPUs, which utilize cache blocking, register tiling, instruction scheduling tuning strategies, this paper identifies and exploits several tuning strategies that are unique for graphics hardware. these tuning strategies include optimizing for multiple-render-targets, SIMD instructions with data packing, overcoming limitations on instruction count and dynamic branch instruction. the generated implementations have comparable performance with expert manually tuned version in spite of the significant overhead incurred due to the use of the high-level BrookGPU language.

关键词： Graphics Hardware Computer architecture Signal processing algorithms Sparse matrices Central processing Unit Software performance Programming profession Pipeline processing High performance computing

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CGMgraph/CGMlib: Implementing and testing cgm graph algorithms on PC clusters and shared memory machines

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international JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2005年第1期19卷 81-97页

作者： Chan, A Dehne, F Taylor, R Fayetteville State Univ Dept Math & Comp Sci Fayetteville NC 28301 USA Griffith Univ Sch ICT Brisbane Qld 4111 Australia Carleton Univ Sch Comp Sci Ottawa ON K1S 5B6 Canada

In this paper, we present CGMgraph, the first integrated library of parallel graph methods for PC clusters based on Coarse Grained Multicomputer (CGM) algorithms. CGMgraph implements parallel methods for various graph problems. Our implementations of deterministic list ranking, Euler tour, connected components, spanning forest, and bipartite graph detection are, to our knowledge, the first efficient implementations for PC clusters. Our library also includes CGMlib, a library of basic CGM tools such as sorting, prefix sum, one-to-all broadcast, all-to-one gather, h-Relation, all-to-all broadcast, array balancing, and CGM partitioning. Both libraries are available for download at http: //www. scs. carleton. ca/similar tocgm. In the experimental part of this paper, we demonstrate the performance of our methods on four different architectures: a gigabit connected high performance PC cluster, a smaller PC cluster connected via fast ethernet, a network of workstations, and a shared memory machine. Our experiments show that our library provides good parallel speedup and scalability on all four platforms. the communication overhead is, in most cases, small and does not grow significantly with an increasing number of processors. this is a very important feature of CGM algorithms which makes them very efficient in practice.

关键词： coarse-grained multiprocessor graph algorithms library parallel algorithms implementation processor cluster

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