this paper proposes a new parallel implementation scheme to increase the bit rate of a cyclic code decoder. the principle is based on the partition of the architecture into a syndrome calculation block and an error ac...
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this paper proposes a new parallel implementation scheme to increase the bit rate of a cyclic code decoder. the principle is based on the partition of the architecture into a syndrome calculation block and an error accumulation block, in order to eliminate the error "decision" function from the feedback loop in the cyclic code decoder. this approach allows effective parallel and pipelining techniques to be applied. the resulting high speed parallel architecture has been implemented on FPGA devices from the Altera/Flex10KE family. Bit rates up to 6.8 Gbits/s have been achieved withparallelism level up to 31.
We present a method for co-partitioning affine indexed algorithms resulting in a processor array with an optimized data-reuse. through this method, a memory hierarchy with an optimized data transfer is derived which a...
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We present a method for co-partitioning affine indexed algorithms resulting in a processor array with an optimized data-reuse. through this method, a memory hierarchy with an optimized data transfer is derived which allows a significant reduction of the power consumption caused by memory accesses. Apart from former design flows which begin with a space-time transformation, we start withthe co-partitioning of the iteration space. this allows an adaption of the resulting processor array towards the constraints of the target architecture at the beginning of the design. We illustrate our method for the full search motion estimation algorithm which bears a high potential of data-reuse.
this paper proposes a parallel architecture for estimation of the motion of an underwater robot. It is well known that image processing requires a huge amount of computation, mainly at low-level processing where the a...
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this paper proposes a parallel architecture for estimation of the motion of an underwater robot. It is well known that image processing requires a huge amount of computation, mainly at low-level processing where the algorithms are dealing with a great number of data. In a motion estimation algorithm, correspondences between two images have to be solved at the low level. In the underwater imaging, normalised correlation can be a solution in the presence of non-uniform illumination. Due to its regular processing scheme, parallel implementation of the correspondence problem can be an adequate approach to reduce the computation time. Taking into consideration the complexity of the normalised correlation criteria, a new approach using parallel organisation of every processor from the architecture is proposed.
Dehne et al. present a BSP/CGM algorithm for computing a spanning tree and the connected components of a graph, that requires O(log p) communication rounds, where p is the number of processors. It requires the solutio...
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Inference of large phylogenetic trees with statistical methods is computationally intensive. We recently introduced simple heuristics which yield accurate trees for synthetic as well as real data and are implemented i...
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this paper focuses on genetic optimization and filtering efficiency ofa recently developed class ofWeighted Vector Directional Filters (WVDFs), which minimize the aggregated weighted angular distances between the samp...
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In this paper, we introduce a new interconnection system OMULT (Optical Multi-Trees) using both electronic and optical links among processors. the processors are organized in the form of an n x n array of trees, each ...
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Although many works have reported simulated performance benefits of stream reuse techniques to the scalability of VoD systems, these techniques have been rarely evaluated in practical implementations of scalable VoD s...
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Implementing image-processing systems can require significant effort and resources due to information volume and algorithm complexity. Model integrated computing (MIC) based image processing systems show promise in su...
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Implementing image-processing systems can require significant effort and resources due to information volume and algorithm complexity. Model integrated computing (MIC) based image processing systems show promise in supporting solutions of these complex problems. While MIC has contributed to the advancement of performing complex image processing tasks on parallel-embedded systems, it has not addressed a challenging class of algorithmsthat adapt the image-processing algorithm based on the information or state of the image processing system. this proposed effort addresses creating an adaptive image-processing environment based on MIC that allows solutions of complex image processing problems to be built and executed rapidly. this effort involves creating a new modeling representation for image processing adaptation mechanisms. the proposed MIC-based adaptive image-processing environment generates a solution given the modeling constraints and executes it on a number of hardware architectures.
this work presents the design of a high speed (255, 239) Reed-Solomon (RS) coder and decoder (CODEC) for high-speed application systems, adopting the proposed high-speed GF(2/sup m/) arithmetic elements, such as a sta...
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ISBN:
(纸本)0780386019
this work presents the design of a high speed (255, 239) Reed-Solomon (RS) coder and decoder (CODEC) for high-speed application systems, adopting the proposed high-speed GF(2/sup m/) arithmetic elements, such as a standard-basis GF(2/sup m/) multiplier mid inversion circuit. these GF(2/sup m/) arithmetic elements are designed in semi-systolic and parallelprocessing architecture to improve performance in the sense of speed, complexity, and latency. When using 0.25 /spl mu/m CMOS technology, we implement the designed (255,239) RS CODEC, operated at clock speed of 580 MHz for worst-case environment, and at throughput rate of 4.64 Gbits/s with 181.717 gates in 654 latency, with a supply voltage of 2.5 V.
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