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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

共 2792 条记录，以下是2321-2330 订阅

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Reactive prohibition-based ant colony optimization (RPACO): a new parallel architecture for constrained clique sub-graphs

Reactive prohibition-based ant colony optimization (RPACO): ...

引用

international conference on Tools for Artificial Intelligence (ICTAI)

作者： S.M. Youssef D.G. Elliman School of Computer Science and IT University of Nottingham UK

We introduce a new algorithm that combines the stigmergetic capabilities of the ant colony optimization (AGO) with local search heuristics to solve the maximum and maximum-weighted clique problem. Our new algorithm: A reactive prohibition-based ant colony optimization (RPACOMCP), complements the intelligent ant colony search with a prohibition-based diversification technique, where the amount of diversification is determined in an automated way through a feedback (history-sensitive) scheme. Based on prohibition, some local moves are temporarily prohibited in order to avoid repeated cycles in the search trajectory and to explore new parts of the total search space. Diversification could be enforced and the ACO search continued beyond local optimal points. One of the main advantages of this approach is the use of parallelism both to have a number of ant colonies searching simultaneously and to have a function distribution of local search procedures. this architecture thus provides a powerful tool to tackle difficult problems using all available processing power. the algorithm is tested on many representative DIMACS benchmark graph instances and results are compared with GLS [E. Marchiori, (2002)], a genetic local search approach for MCP. It is shown that the proposed PACO algorithm finds larger cliques in reasonable time, on average, on a wide majority of benchmark instances of the DIMACS library, even though it does not reach the best known results on a few benchmark instances. We also showed that the PACO algorithm outperforms the nonprohibition version on most hard graph instances.

关键词： Ant colony optimization parallel architectures Feedback Computer science Benchmark testing Genetics Heuristic algorithms Computer architecture parallel processing Libraries

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A high parallel-pipelined real-time estimation architecture for MPEG-4 simple profile

A high parallel-pipelined real-time estimation architecture ...

引用

Asia-Pacific conference on Communications

作者： Dongjun Lou Ningyi Xu Xiaokang Lin Department of Electronic Engineering Tsinghua University Beijing China Graduate School at Shenzhen Tsinghua University Beijing China

ISBN: (纸本)0780386019

A high parallel-pipelined VLSI architecture for MPEG-4 motion estimation is proposed in this paper, searching for the best match to the reference block by full search block matching algorithm to enhance the video quality. It possesses the characteristics of low embedded memory, low clock rate with high accuracy, and flexibility to adapt different search window size, aiming at both mobile applications and high-definition fields. Full search block matching algorithm has been mapped onto this architecture using an optimized processing element array that has the ability to evaluate the motion vectors of CIF video timely at 8 MHZ clock rate with only 5 Kb embedded memory. the proposed architecture has been prototyped, simulated and synthesized for 0.35 /spl mu/m CMOS technology using FUJITSU CE66 cells. the prototyped architecture consumes 190.3 mW with 3.3 V supply voltage and has core area of 5.52 mm/sup 2/ with 5 layers of metal. It largely improves the performance to more than 33 times faster with only 34.6% more core area cost than the reference motion estimation architecture of MPEG-4 part 9.

关键词： MPEG 4 Standard Motion estimation Clocks CMOS technology Very large scale integration Memory architecture Virtual prototyping Prototypes Voltage Costs

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Adding limited reconfigurability to superscalar processors 04

Adding limited reconfigurability to superscalar processors

引用

international conference on parallel Architecture and Compilation Techniques (PACT)

作者： M. Epalza P. Ienne D. Mlynek Signal Processing Institute Switzerland Processor Architecture Laboratory Switzerland Swiss Federal Institute of Technology Lausanne Switzerland

ISBN: (纸本)9780769522296

When adding reconfigurability to custom hardware, one must take great care that the reduction in speed due to the reconfigurable logic should not cancel out the gains obtained by reconfiguration. these gains are greatest in very specific and computation-intensive applications, and lessen as the applications become more general and heterogeneous. In the case of superscalar processors, this leads to limiting the amount of reconfigurability to precise changes in existing functional units instead of adding a fully configurable functional unit. We present a detailed study of the modifications necessary in a superscalar processor to allow an FPU to be dynamically reconfigured as several ALUs with a minimal increase in the latency of these functional units. the timing of the FPU's multiplier tree and the decision about reconfiguration are exposed. As there is more than one simple unit involved, this decision is more global than a cycle-by-cycle reconfiguration and must be made for a longer period of time. We discuss possible policies for the dynamic reconfiguration decisions. the results show interesting gains of up to 56% in the best cases, and average gains of 10%, on typical architectures over a wide range of applications.

关键词： Reconfigurable logic Field programmable gate arrays Hardware Signal processing Delay Automatic control Switches Computer applications Limiting Timing

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Extracting an explicitly data-parallel representation of image-processing programs 10

Extracting an explicitly data-parallel representation of ima...

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10th Working conference on Reverse Engineering (WCRE 2003)

作者： Baumstark, L Guler, M Wills, L Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)0769520278

Our research goal is to retarget image processing programs written in sequential languages (e.g., C) to architectures with data-parallel processing capabilities. Image processing algorithms are often inherently data-parallel, but the artifacts imposed by the sequential programming language (e.g., loops, pointer variables, linear address spaces) can obscure the parallelism and prohibit generation of efficient parallel code. this paper proposes a program representation and pattern-recognition approach for generating a data-parallel program specification from sequential source code. the representation is based on an extension of the multidimensional synchronous dataflow (MDSDF) model of computation. Central to extracting this representation front code is understanding the mapping between iterations and array variables in the source code and the operations over array regions (e.g., rows, columns, tiled blocks) that they implement. Examples are presented to illustrate this mapping, and a set of patterns for recognizing these regions are proposed. the correctness of the retargeted MDSDF specifications are validated and the potential speedup from parallel execution shown.

关键词： program transformation parallelization program representation SIMD pattern-recognition

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Design and implementation of a reconfigurable architecture for DSP 5

Design and implementation of a reconfigurable architecture f...

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5th international conference on ASIC

作者： Yang, Y Mao, ZG Lai, FC Zhao, B Xia, YF Harbin Inst Technol Ctr Microelect Harbin 150001 HeiLongJiang Peoples R China

ISBN: (纸本)078037889X

To accelerate the execution of most DSP(Digital Signal processing) algorithms such as FFT, FIR, Vector operations, while keeping the flexibility of the chip, a reconfigurable architecture (named ReDAr) for DSP is proposed and implemented, and finally will be applied to the Radar system of Automatic Navigation Equipment. By analyzing these algorithms, the structure of Reconfigurable processing Element (RPE), the Crossbar interconnect network, the Memory organization. the host controlling strategy, and the data sequencing scheme of the architecture are conceived. and parts of them, including the RPE, Crossbar. data sequencer, are reconfigurable. After configuration. it can be interconnected into a parallel and pipelined framework. closely matching the algorithms and like a dedicated hardware. By simulation. the performances of these algorithms mapped onto this architecture are comparative to algorithm-specific chips in market, and satisfy the requirement of the targeted application.

关键词： radar signal processing radionavigation reconfigurable architectures parallel processing pipeline processing fast Fourier transforms FIR filters ReDAr reconfigurable architecture DSP algorithms digital signal processing algorithms FFT fast Fourier transform FIR finite impulse response vector operations radar system automatic navigation equipment RPE reconfigurable processing element crossbar interconnect network memory organization data sequencing pipelined framework parallel framework

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Unscheduling, unpredication, unspeculation: Reverse engineering itanium executables 10

Unscheduling, unpredication, unspeculation: Reverse engineer...

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10th Working conference on Reverse Engineering (WCRE 2003)

作者： Snavely, N Debray, S Andrews, G Univ Arizona Dept Comp Sci Tucson AZ 85721 USA

ISBN: (纸本)0769520278

EPIC (Explicitly parallel Instruction Computing) architectures, exemplified by the Intel Itanium, support a number of advanced architectural features, such as explicit instruction-level parallelism, instruction predication, and speculative loads from memory. However, compiler optimizations to take advantage of such architectural features can profoundly restructure the program's code, making it potentially difficult to reconstruct the original program logic from an optimized Itanium executable. this paper describes-techniques to undo some of the effects of such optimizations and thereby improve the quality of reverse engineering such executables.

关键词： Computer aided instruction Computer architecture Computer science Concurrent computing Delay Logic Optimizing compilers parallel processing Pipelines Reverse engineering

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architectures and algorithms for multimedia applications 9th

Architectures and algorithms for multimedia applications

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9th international Euro-Par conference on parallel processing, Euro-Par 2003

作者： Ahmad, Ishfaq Jonker, Pieter Schmidt, Bertil Uhl, Andreas

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10th international Symposium on String processing and Information Retrieval, SPIRE 2003

10th International Symposium on String Processing and Inform...

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10th international Symposium on String processing and Information Retrieval, SPIRE 2003

ISBN: (纸本)3540201777

the proceedings contain 29 papers. the special focus in this conference is on Web algorithms, Bit-parallel algorithms, Compression and Music Retrieval. the topics include: Link information as a similarity measure in web classification;a three level search engine index based in query log distribution;alternative algorithms for bit-parallel string matching;bit-parallel approximate string matching algorithms with transposition;processing of Huffman compressed texts with a super-alphabet;an optimized compression code for natural language text databases;linear-time off-line text compression by longest-first substitution;structural contexts model for improving compression in semistructured text databases;ranking structured documents using utility theory in the Bayesian network retrieval model;an empirical comparison of text categorization methods;improving text retrieval in medical collections through automatic categorization;flexible and efficient bit-parallel techniques for transposition invariant approximate matching in music retrieval;analysis and evaluation of a Turkish stemming algorithm;non-adjacent digrams improve matching of cross-lingual spelling variants;the implementation and evaluation of a lexicon-based stemmer;new refinement techniques for longest common subsequence algorithms;distributed query processing using suffix arrays;bit filtration technique for approximate string join in biological databases;using wordnet for word sense disambiguation to support concept map construction;memory-adaptative dynamic spatial approximation trees and large edit distance with multiple block operations.

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Image quilting for texture synthesis: A revisit & a variation 4

Image quilting for texture synthesis: A revisit & a variatio...

引用

Joint conference of the 4th international conference on Information, Communications and Signal processing/4th Pacific-Rim conference on Multimedia (ICICS-PCM 2003)

作者： O'Brien, JT Wickramanayake, DS Edirisinghe, EA Bez, HE Loughborough Univ Technol Parallel Algorithms & Architectures Res Ctr Loughborough LE11 3TU Leics England

ISBN: (纸本)0780381858

the current trends in computer animations, virtual reality and augmented reality applications have resulted in the problem of texture synthesis receiving considerable attention from the computer graphics and image processing research community. In this paper we revisit the well-known texture synthesis method, image quilting, first proposed by Efros and Freeman and propose improvements to its algorithms and implementation. Further, we outline its application within a multi-resolution framework, particularly suited for modern imaging applications associated with compressed image data. We provide experimental results to prove the effectiveness of the proposed modifications and variation.

关键词： texture synthesis image quilting rendering image processing

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Mapping and scheduling for architecture exploration of networking SoCs 16

Mapping and scheduling for architecture exploration of netwo...

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16th international conference on VLSI Design/2nd international conference on Embedded Systems Design

作者： Wild, T Foag, J Pazos, N Brunnbauer, W Tech Univ Munich Inst Integrated Circuits D-80290 Munich Germany

ISBN: (纸本)0769518680

this paper describes two different approaches to optimize the performance of SoC architectures in the architecture exploration phase. Both solve the problem to map and schedule a task graph on a target architecture under special consideration of on-chip communications. A constructive algorithm is presented that extends previous work by taking into account potential data transfers in the future. the second approach is a recursive procedure that is based on local search techniques in a specially defined neighborhood of the critical path. Simulated annealing and tabu search are used as search algorithms. Both approaches find solutions with better performance than established methodologies. the recursive technique leads to superior results than the constructive approach, however is limited to small and mid-sized problems, whereas the constructive algorithm is not limited by this issue.

关键词： Constraint optimization Context Delay NP-complete problem parallel processing Partitioning algorithms Polynomials Proposals Scheduling Very large scale integration

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