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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"
2792 条 记 录,以下是2411-2420 订阅
排序:
Comparison of 32-bit multipliers for various performance measures
Comparison of 32-bit multipliers for various performance mea...
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international conference on Microelectronics, ICM
作者: S. Shah A.J. Al-Khalili D. Al-Khalili Dept. of Electr. & Comput. Eng. Concordia Univ. Montreal Que. Canada Concordia University Montreal QC CA
Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tre... 详细信息
来源: 评论
DOA Estimation Method Based on Neural Network
DOA Estimation Method Based on Neural Network
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international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)
作者: Zhang Ping Department of Electronic Technology Engineering University of CAPF Xi'an China
Traditional signal direction of arrival (DOA) estimation algorithm has exist some problems, such as a large amount of calculation and slow convergence speed. In this paper, neural network method is used to improve the... 详细信息
来源: 评论
A model-based self-adaptive approach to image processing
A model-based self-adaptive approach to image processing
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international conference and Workshop on Engineering of Computer-Based Systems
作者: J. Nichols T. Bapty Institute for Software Integrated Systems Nashville TN USA
Implementing image-processing systems can require significant effort and resources due to information volume and algorithm complexity. Model integrated computing (MIC) based image processing systems show promise in su... 详细信息
来源: 评论
Leverage cache replacement policy in multicore processors
Leverage cache replacement policy in multicore processors
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IEEE international conference on Intelligent Computer Communication and processing (ICCP)
作者: Marius Geanta Lavinia Ghica Nicolae Tapus Bucharest Romania “Politehnica” University of Bucharest Bucharest Romania Computer Science Departament “Politehnica” University of Bucharest Bucharest Romania
Computer hardware is currently moving towards heavily parallelized architectures with multiprocessors, multicore and chip multithreaded designs. Cache memory, the fastest component of the memory hierarchy, adapts to t... 详细信息
来源: 评论
Evaluating the Performance and Accuracy Impact of Trace Generation to the BigSim Emulator
Evaluating the Performance and Accuracy Impact of Trace Gene...
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international conference on Computer and Information Technology (CIT)
作者: Yonggang Che Chuanfu Xu Pingjing Lu National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China
this paper quantitatively studies the trace effects to the performance and accuracy of the BigSim Emulator, a scalable parallel emulator for large-scale computers. To assess the accuracy effect we modify the emulator ... 详细信息
来源: 评论
A FPGA real-time stereo vision system with luminance control and projected pattern
A FPGA real-time stereo vision system with luminance control...
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international conference on ASIC
作者: Yuan Xu Haodong Yao Liwei Gong Mingcheng Zhu Robert K. F. Teng Shenzhen Key Lab of Advanced Communication and Information Processing College of Information Engineering Shenzhen University 518000 China Department of Electrical Engineering California State University Long Beach USA
this paper presents a real-time stereo video processing system based on FPGA. the system takes rectification and histogram equalization as its pre-processing, and the depth detection of this system is using generalize... 详细信息
来源: 评论
Trends of Intel MIC Application In Bioinformatics
Trends of Intel MIC Application In Bioinformatics
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IEEE international conference on Software Engineering and Service Sciences (ICSESS)
作者: Xinyi Wang Cangshuai Wu Zhen Huang Collage of Computer National University of Defense Technology Changsha China
With the rapid development of next-generation sequencing (NGS) technology, the ever-increasing biological sequence data poses a tremendous challenge to data processing. therefore, there is an urgent need for intensive... 详细信息
来源: 评论
A FPGA-based parallel Architecture for Scalable High-Speed Packet Classification
A FPGA-based Parallel Architecture for Scalable High-Speed P...
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IEEE international conference on Application-specific Systems, architectures and Processors
作者: Weirong Jiang Viktor K. Prasanna Ming Hsieh Department of Electrical Engineering University of Southern California
Multi-field packet classification is a critical function that enables network routers to support a variety of applications such as firewall processing, Quality of Service differentiation, traffic billing, and other va... 详细信息
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Querying Historical Cohesive Subgraphs over Temporal Bipartite Graphs  40
Querying Historical Cohesive Subgraphs over Temporal Biparti...
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40th IEEE international conference on Data Engineering, ICDE 2024
作者: Li, Shunyang Wang, Kai Lin, Xuemin Zhang, Wenjie He, Yizhang Yuan, Long University of New South Wales Australia Antai College of Economics and Management Shanghai Jiao Tong University China Nanjing University of Science and Technology China
In many real-world scenarios, relationships between two different entities can be naturally represented as bipartite graphs, such as author-paper, user-item, and people-location. Cohesive subgraph search, which aims t... 详细信息
来源: 评论
Efficient implementation of 3780-point FFT on a 16-core processor
Efficient implementation of 3780-point FFT on a 16-core proc...
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international conference on ASIC
作者: Haofan Yang Kedong Chen Shengqiong Xie Ming-e Jing Zhiyi Yu Xiaoyang Zeng State Key Laboratory of ASIC & System Fudan University Shanghai China Shanghai University of Engineering Science
the 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. In this paper, we proposed an effic... 详细信息
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