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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Comparison of 32-bit multipliers for various performance measures

Comparison of 32-bit multipliers for various performance mea...

引用

international conference on Microelectronics, ICM

作者： S. Shah A.J. Al-Khalili D. Al-Khalili Dept. of Electr. & Comput. Eng. Concordia Univ. Montreal Que. Canada Concordia University Montreal QC CA

ISBN: (纸本)9643600572

Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tree multiplier, combined modified Booth-Wallace tree multiplier and twin pipe serial parallel multiplier. Comparison is based on synthesis results obtained by synthesizing all multiplier architectures towards FPGA.

关键词： Signal processing algorithms Adders Energy consumption Field programmable gate arrays Digital signal processing Very large scale integration parallel processing Silicon Integrated circuit interconnections Routing

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DOA Estimation Method Based on Neural Network

DOA Estimation Method Based on Neural Network

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international conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Zhang Ping Department of Electronic Technology Engineering University of CAPF Xi'an China

Traditional signal direction of arrival (DOA) estimation algorithm has exist some problems, such as a large amount of calculation and slow convergence speed. In this paper, neural network method is used to improve the performance of DOA estimation. Due to the fact that BP neural network is inclined to be trapped in local minimum point, particle swarm optimization (PSO) algorithm is applied to optimization the weights and threshold. the model of DOA estimation based on PSO-BP neural network is constructed and trained. Simulation results show that, compared with classical RBFNN method and traditional MUSIC algorithm, the optimized BP neural network method has higher estimation accuracy and real-time performance.

关键词： Estimation Direction-of-arrival estimation Biological neural networks Covariance matrices Arrays Array signal processing

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A model-based self-adaptive approach to image processing

A model-based self-adaptive approach to image processing

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international conference and Workshop on Engineering of Computer-Based Systems

作者： J. Nichols T. Bapty Institute for Software Integrated Systems Nashville TN USA

Implementing image-processing systems can require significant effort and resources due to information volume and algorithm complexity. Model integrated computing (MIC) based image processing systems show promise in supporting solutions of these complex problems. While MIC has contributed to the advancement of performing complex image processing tasks on parallel-embedded systems, it has not addressed a challenging class of algorithms that adapt the image-processing algorithm based on the information or state of the image processing system. this proposed effort addresses creating an adaptive image-processing environment based on MIC that allows solutions of complex image processing problems to be built and executed rapidly. this effort involves creating a new modeling representation for image processing adaptation mechanisms. the proposed MIC-based adaptive image-processing environment generates a solution given the modeling constraints and executes it on a number of hardware architectures.

关键词： Image processing conferences Systems engineering and theory

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Leverage cache replacement policy in multicore processors

Leverage cache replacement policy in multicore processors

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IEEE international conference on Intelligent Computer Communication and processing (ICCP)

作者： Marius Geanta Lavinia Ghica Nicolae Tapus Bucharest Romania “Politehnica” University of Bucharest Bucharest Romania Computer Science Departament “Politehnica” University of Bucharest Bucharest Romania

ISBN: (纸本)9781509039005

Computer hardware is currently moving towards heavily parallelized architectures with multiprocessors, multicore and chip multithreaded designs. Cache memory, the fastest component of the memory hierarchy, adapts to this new kind of parallel systems in order to provide the promised performance increase. Current cache designs have limitations that can be transformed into optimization opportunities both in hardware and software. this paper provides a detailed research of cache performance in multicore processors, considering critical hardware aspects. A new solution is proposed to improve the current performance: an optimized replacement policy for the shared cache level. From experiments run on four and eight core setups in a multicore simulator, the proposed enhancements achieve up to 30% execution speed increase over the default setup.

关键词： Multicore processing Program processors Hardware throughput Approximation algorithms Electronics packaging

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Evaluating the Performance and Accuracy Impact of Trace Generation to the BigSim Emulator

Evaluating the Performance and Accuracy Impact of Trace Gene...

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international conference on Computer and Information Technology (CIT)

作者： Yonggang Che Chuanfu Xu Pingjing Lu National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

this paper quantitatively studies the trace effects to the performance and accuracy of the BigSim Emulator, a scalable parallel emulator for large-scale computers. To assess the accuracy effect we modify the emulator code to collect the predicted computation time. Four MPI programs with different computation to communication ratios are used as benchmarks. the emulation time and the predicted computation time, both when trace generation are enabled and disabled, are collected on two parallel host machines. the results show that although the BigSim Emulator only traces communication events and dependencies, trace generation still evidently degrades the emulation performance for programs with high communication to computation ratios. Trace generation also significantly affects the accuracy of the predicted computation time for communication intensive programs, which is an issue that can not be overlooked.

关键词： Emulation Accuracy Runtime Benchmark testing Program processors Predictive models Jacobian matrices

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A FPGA real-time stereo vision system with luminance control and projected pattern

A FPGA real-time stereo vision system with luminance control...

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international conference on ASIC

作者： Yuan Xu Haodong Yao Liwei Gong Mingcheng Zhu Robert K. F. Teng Shenzhen Key Lab of Advanced Communication and Information Processing College of Information Engineering Shenzhen University 518000 China Department of Electrical Engineering California State University Long Beach USA

this paper presents a real-time stereo video processing system based on FPGA. the system takes rectification and histogram equalization as its pre-processing, and the depth detection of this system is using generalized census transform and block matching method. With the help of on-line generated projected pattern by the pattern controller inside FPGA, this system can be used in various environments. the median filter is used as the post-processing step of depth map. In comparison to the software solution method, this system takes the advantage of the parallel nature of FPGA and got higher speed in generating the depth map. therefore, it can be applied to the applications demanded for better performance.

关键词： Histograms Field programmable gate arrays Real-time systems Stereo vision Hardware Transforms Hamming distance

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Trends of Intel MIC Application In Bioinformatics

Trends of Intel MIC Application In Bioinformatics

引用

IEEE international conference on Software Engineering and Service Sciences (ICSESS)

作者： Xinyi Wang Cangshuai Wu Zhen Huang Collage of Computer National University of Defense Technology Changsha China

ISBN: (数字)9781728109459

ISBN: (纸本)9781728109466

With the rapid development of next-generation sequencing (NGS) technology, the ever-increasing biological sequence data poses a tremendous challenge to data processing. therefore, there is an urgent need for intensive computing power to speed up the data analysis process. Among the state-of-the-art parallel accelerators, Intel Xeon Phi coprocessor is a bootable host processor based on Intel Many Integrated Core (MIC) architecture that provides massive parallelism and vectorization to support the most demanding high-performance computing (HPC) applications. the underlying x86 architecture supports common parallel programming standard libraries that provide familiarity and flexibility to transplant existing code to heterogeneous computing environments. In addition, it delivers three usage model including native, offload and symmetric models to solve different application problems on the MIC-based neo-heterogeneous architectures. Currently, Intel Xeon Phi is becoming a common parallel computing platform for decreasing the computational cost of the most demanding processes in bioinformatics. To help researchers make better use of MIC, we reviewed the MIC-based bioinformatics applications, providing a comprehensive guideline for bioinformatics researchers to apply MIC in their own fields.

关键词： Microwave integrated circuits Computational modeling Bioinformatics Coprocessors Computer architecture parallel processing Acceleration

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A FPGA-based parallel Architecture for Scalable High-Speed Packet Classification

A FPGA-based Parallel Architecture for Scalable High-Speed P...

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IEEE international conference on Application-specific Systems, architectures and Processors

作者： Weirong Jiang Viktor K. Prasanna Ming Hsieh Department of Electrical Engineering University of Southern California

ISBN: (纸本)9781424445523

Multi-field packet classification is a critical function that enables network routers to support a variety of applications such as firewall processing, Quality of Service differentiation, traffic billing, and other value added services. Explosive growth of Internet traffic requires the future packet classifiers be implemented in hardware. However, most of the existing packet classification algorithms need large amount of memory, which inhibits efficient hardware implementations. this paper exploits the modern FPGA technology and presents a partitioning-based parallel architecture for scalable and high-speed packet classification. We propose a coarse-grained independent sets algorithm and then combine it seamlessly with the cross-producting scheme. After partitioning the original rule set into several coarse-grained independent sets and applying the cross-producting scheme for the remaining rules, the memory requirement is dramatically reduced. Our FPGA implementation results show that our architecture can store 10K real-life rules in a single state-of-the-art FPGA while consuming a small amount of on-chip resources. Post place and route results show that the design sustains 90Gbps throughput for minimum size (40 bytes) packets, which is more than twice the current backbone network link rate.

关键词： FPGA Packet classification Partitioning

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Querying Historical Cohesive Subgraphs over Temporal Bipartite Graphs 40

Querying Historical Cohesive Subgraphs over Temporal Biparti...

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40th IEEE international conference on Data Engineering, ICDE 2024

作者： Li, Shunyang Wang, Kai Lin, Xuemin Zhang, Wenjie He, Yizhang Yuan, Long University of New South Wales Australia Antai College of Economics and Management Shanghai Jiao Tong University China Nanjing University of Science and Technology China

ISBN: (纸本)9798350317152

In many real-world scenarios, relationships between two different entities can be naturally represented as bipartite graphs, such as author-paper, user-item, and people-location. Cohesive subgraph search, which aims to find densely connected subgraphs, is a popular research topic on bipartite graphs. While various cohesive subgraph models are proposed on bipartite graphs, none of them consider the temporal dimension, which expresses dynamic changes occurring in cohesive subgraphs over time. In this paper, we propose the first cohesive subgraph model (α, β, T )-core on temporal bipartite graphs. Given degree constraints α and β, as well as a time window T = [ts, te], (α, β, T )-core guarantees that each vertex in the upper or lower layer has at least α or β neighbors, respectively, within the snapshot over the time window T . An intuitive solution to compute the (α, β, T )-core is to iteratively remove the vertices that do not satisfy the degree constraints in the snapshot, which suffers from inefficiency and is impractical on large temporal bipartite graphs. therefore, we turn to index-based methods to enhance query performance. To support efficient arbitrary (α, β, T )-core queries, we propose a vertex-partitioning historical index called VH-Index and a time-partitioning historical index called th-Index. Note that these two indexes need to store (α, β, T )-core for each possible combination of α, β, and T and incur large construction costs. therefore, we further propose a temporal intersection index called th∗-Index to strike a balance between the efficiency of query processing and the space cost of the index. We develop both sequential and parallel algorithms for efficiently constructing the temporal-intersection index. Extensive experiments are conducted on 10 real-world temporal bipartite graphs to validate the effectiveness of the (α, β, T )-core model and the efficiency of our proposed algorithms. © 2024 IEEE.

关键词： Query processing

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Efficient implementation of 3780-point FFT on a 16-core processor

Efficient implementation of 3780-point FFT on a 16-core proc...

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international conference on ASIC

作者： Haofan Yang Kedong Chen Shengqiong Xie Ming-e Jing Zhiyi Yu Xiaoyang Zeng State Key Laboratory of ASIC & System Fudan University Shanghai China Shanghai University of Engineering Science

the 3780-point FFT is a main component of the time domain synchronous OFDM (TDS-OFDM) system in the Chinese Digital Multimedia/TV Broadcasting-Terrestrial (DMB-T) national standard. In this paper, we proposed an efficient implementation for 3780-point FFT on multi-core processors, which makes full use of the parallelism of FFT application and multi-core system. Experiment results demonstrate that multi-core 3780-point FFT implementation not only achieves a speedup ratio of 6.475 over single core implementation but also maintains a great flexibility compared with ASIC implement.

关键词： parallel processing Pipelines Algorithm design and analysis Discrete Fourier transforms Multicore processing Multimedia communication Standards

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