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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"
2747 条 记 录,以下是2421-2430 订阅
排序:
A high-speed VLSI fuzzy logic controller with pipeline architecture
A high-speed VLSI fuzzy logic controller with pipeline archi...
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IEEE international conference on Fuzzy Systems (FUZZ-IEEE)
作者: Shih-Hsu Huang Jian-Yuan Lai Department of Electronic Engineering Chung Yuan Christian University Chungli Taiwan
We present a high-speed VLSI fuzzy logic controller, which is well suitable for real time applications. the main distinction of our approach is that it may complete the max-min calculation within one clock cycle. the ... 详细信息
来源: 评论
Comparing and combining read miss clustering and software prefetching
Comparing and combining read miss clustering and software pr...
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international conference on parallel Architecture and Compilation Techniques (PACT)
作者: V.S. Pai S.V. Adve Electrical and Computer Engineering Rice University Houston TX USA Computer Science University of Illinois Urbana-Champaign IL USA
A recent latency tolerance technique, read-miss clustering, restructures code to send demand-miss references in parallel to the underlying memory system. An alternative, widely-used latency tolerance technique is soft... 详细信息
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VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding
VLSI-based parallel architecture for block-matching motion e...
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: Donglai Xu J. Bentley School of Science and Technology University of Teesside Middlesbrough UK
In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm... 详细信息
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A massively parallel architecture for linear machine code genetic programming  4th
A massively parallel architecture for linear machine code ge...
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4th international conference on Evolvable Systems: From Biology to Hardware, ICES 2001
作者: Eklund, Sven E. Dalama University Sweden
Over the last decades Genetic algorithms (GA) and Genetic Programming (GP) have proven to be efficient tools for a wide range of applications. However, in order to solve human-competitive problems they require large a... 详细信息
来源: 评论
Power exploration of parallel embedded architectures implementing data-reuse transformations
Power exploration of parallel embedded architectures impleme...
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: N. Kavvadias A. Zanikopoulos C. Voliotidis S. Kougia A. Chatzigeorgiou N. Zervas S. Nikolaidis Electronics and Computers Division Department of Physics Aristotle University of Thessaloniki Thessaloniki Greece VLSI Design Laboratory Department of Electrical Engineering University of Patras Patras Greece
Efficient use of data-reuse transformations combined with a custom memory hierarchy that exploits the temporal locality of data related memory accesses can have a significant impact on system power consumption, especi... 详细信息
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On area-efficient low power array multipliers
On area-efficient low power array multipliers
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IEEE international conference on Electronics, Circuits and Systems (ICECS)
作者: Yuke Wang Yingtao Jiang E. Sha Department of Computer Science University of Texas Dallas Richardson TX USA
Multiplication is one of the most critical operations in many computational systems. In this paper, we present an improved architecture for a multiplexer-based multiplication algorithm. Also through intensive HSPICE s... 详细信息
来源: 评论
algorithms & architectures For parallel processing, 4th Intl Conf
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2000年
作者: Andrzej Marian Goscinski Horace Ho Shing Ip
ICA3PP 2000 was an important conference that brought together researchers and practitioners from academia, industry and governments to advance the knowledge of parallel and distributed computing. the proceedings const... 详细信息
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Evolution of DSP architectures: towards parallelism exploitation
Evolution of DSP architectures: towards parallelism exploita...
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10th Mediterranean Electrotechnical conference (MALECON2000)
作者: Sernec, R. Zajc, M. Tasic, J. IPS Ljubljana Slovenia
this paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and recently adopted some very sophisticated parallelism extraction tech... 详细信息
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Generation of scheduling functions supporting LSGP-partitioning
Generation of scheduling functions supporting LSGP-partition...
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12th IEEE international conference on Application-Specific Systems, architectures, and Processors
作者: Fimmel, D Tech Univ Dresden Dept Elect Engn IEE D-8027 Dresden Germany
In this paper we present an approach to determine scheduling functions suitable for the design of processor arrays. the considered scheduling functions support a followed LSGP-partitioning of the processor array by al... 详细信息
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architectures and algorithms for multimedia applications  6
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6th international Euro-Par 2000 conference
作者: Schimmler, M
the emergence of multimedia technology in recent years is strongly driven by an enormous commercial potential. For the scientific community this development is interesting because a number of attractive disciplines fo...
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