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检索条件"任意字段=10th International Conference on Algorithms and Architectures for Parallel Processing"

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Field programmable gate array design for an application specific signal processing algorithms

Field programmable gate array design for an application spec...

引用

IEEE international Caracas conference on Devices, Circuits and Systems

作者： W.A. Moreno K. Poladia Center for Microelectronics Research University of South Florida Tampa FL USA

Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. this paper presents a new FPGA architecture suitable for the application specific signal processing algorithms and Wafer-Scale integration (WSI) Technology. the architecture must be designed for versatility, flexibility, high speed, improved logic density, and defect tolerance. the proposed FPGA architecture consists of 2 dimensional array of programmable logic elements based on look-up table, interconnection resources, and input/output (I/O) blocks. the architectural style is similar to the one used in XILINX FPGA architecture. A key variation from the commonly used FPGA is the dual switching scheme employed in the proposed architecture. the design methodology, the design tools, and results obtained by using a Segmented Channel Routing algorithm to map on it a 16 bit parallel multiplier, are presented.

关键词： Field programmable gate arrays Programmable logic arrays Signal processing algorithms Design methodology Logic circuits Manufacturing Prototypes Costs Wafer scale integration Logic design

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A Efficient Algorithm for Molecular Dynamics Simulation on Hybrid CPU-GPU Computing Platforms

A Efficient Algorithm for Molecular Dynamics Simulation on H...

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international conference on Natural Computation, Fuzzy Systems and Knowledge Discovery

作者： Dapu Li Wei Ai Yu Ye Jie Liang College of Information Science and Engineering Hunan University Changsha Hunan 410082 China

ISBN: (纸本)9781509040940

In this article, an efficient parallel algorithm for a hybrid CPU-GPU platform is proposed to enable large-scale molecular dynamics (MD) simulations of the metal solidification process. the results, implemented the parallel algorithm program on the hybrid CPU-GPU platform shows better performance than the program based on previous algorithms running on the CPU cluster platform. By contrast, the total execution time of the new program has been obviously decreased. Particularly, because of the use of the modified load balancing method, the neighbor list update time is approximately zero. the parallel program based on the CUDA+OpenMP model shows a factor of 6 16-core calculation speedups compared to the parallel program based on the MPI+OpenMP model, and the optimal computational efficiency is achieved in the simulation system including 10,000,000 aluminum atoms. Finally, the good consistency between them verifies the correctness of the algorithm efficiently, by comparison of the theoretical results and experimental results.

关键词： Graphics processing units Computational modeling parallel algorithms Mathematical model Runtime Load modeling Heuristic algorithms parallel algorithms Load modeling Runtime Heuristic algorithms Computational modeling Mathematical Model efficient algorithm parallel programming Graphics processing Unit Molecular Dynamics Simulation Platform Simulation Systems execution time

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A hierarchical parallel placement technique based on genetic algorithm

A hierarchical parallel placement technique based on genetic...

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international conference on Intelligent Systems Design and Applications (ISDA)

作者： M. Yoshikawa H. Terai Department of VLSI System Design Ritsumeikan University Japan

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the dominant design phase. this paper discusses a novel performance-driven placement technique. the proposed algorithm based on genetic algorithms (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving chip area, interconnect delay and power consumption. In order to reduce run time, the two kind of parallel processing suitable for hierarchical processing is introduced. Experimental results show improvement comparison with commercial EDA tool.

关键词： Genetic algorithms parallel processing Energy consumption Very large scale integration Delay Timing Semiconductor device modeling Logic arrays Intrusion detection Wiring

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Time Efficient Dual-Field Unit for Cryptography-Related processing

Time Efficient Dual-Field Unit for Cryptography-Related Proc...

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16th IFIP WG 10 5 IEEE international conference on Very Large Scale Integration (VLSI-SoC 2008)

作者： Cilardo, Alessandro Mazzocca, Nicola Univ Naples Federico II Dipartimento Informat & Sistemist I-80125 Naples Italy

ISBN: (纸本)9783642122668

Computational demanding public key cryptographic algorithms, such as Rivest-Shamir-Adlernan (RSA) and Elliptic Curve (EC) cryptosystems, are critically dependent on modular multiplication for their performance. Modular multiplication used in cryptography may be performed in two different algebraic structures, namely GF(N) and GF (2(n)), which normally require distinct hardware solutions for speeding up performance. For both fields, Montgomery multiplication is the most widely adopted solution, as it enables efficient hardware implementations, provided that a slightly modified definition of modular multiplication is adopted. In this paper we propose a novel unified architecture for parallel Montgomery multiplication supporting both GF(N) and GF(2(n)) finite field operations, which are critical for RSA ad ECC public key cryptosystems. the hardware scheme interleaves multiplication and modulo reduction. Furthermore, it relies on a modified Booth recoding scheme for the multiplicand and a radix-4 scheme for the modulus, enabling reduced time delays even for moderately large operand widths. In addition, we present a pipelined architecture based on the parallel blocks previously introduced, enabling very low clock counts and high throughput levels for long operands used in cryptographic applications. Experimental results, based on 0.18 mu m CMOS technology, prove the effectiveness of the proposed techniques, and outperform the best results previously presented in the technical literature.

关键词： Public key cryptography

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Unified weighted label propagation algorithm using connection factor 12th

Unified weighted label propagation algorithm using connectio...

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12th international conference on Advanced Data Mining and Applications, ADMA 2016

作者： Wang, Xin Jian, Songlei Lu, Kai Wang, Xiaoping College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9783319495859

With the social networks getting increasingly larger, fast community detection algorithms like the label propagation algorithm, are attracting more attention. But the label propagation algorithm deals vertices with no proper weight, which leads to the loss in the performance. We propose the connection factor of the vertex to measure its influence on the local connectivity. the connection factor can reveal the topological structure feature, and we propose a unified weight to modify the original label propagation algorithm. Experiments show that our Unified Weighted LPA has an average performance promotion from 5% to 10 %, in the best case more than 30%. © Springer international Publishing AG 2016.

关键词： Population dynamics

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Design for high-speed RS-codec based on Galois-field arithmetics

Design for high-speed RS-codec based on Galois-field arithme...

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Asia-Pacific conference on Communications

作者： Sungsoo Choi Kiseon Kim Kwan-Ho Kim Power Telecommunication Network Research Group Korea Electrotechnology Research Institute Euiwang Kyunggi South Korea Department of Information and Communications Gwangju Institute of Science and Technology Kwangju South Korea

ISBN: (纸本)0780386019

this work presents the design of a high speed (255, 239) Reed-Solomon (RS) coder and decoder (CODEC) for high-speed application systems, adopting the proposed high-speed GF(2/sup m/) arithmetic elements, such as a standard-basis GF(2/sup m/) multiplier mid inversion circuit. these GF(2/sup m/) arithmetic elements are designed in semi-systolic and parallel processing architecture to improve performance in the sense of speed, complexity, and latency. When using 0.25 /spl mu/m CMOS technology, we implement the designed (255,239) RS CODEC, operated at clock speed of 580 MHz for worst-case environment, and at throughput rate of 4.64 Gbits/s with 181.717 gates in 654 latency, with a supply voltage of 2.5 V.

关键词： Arithmetic Codecs Delay CMOS technology Reed-Solomon codes Decoding Circuits parallel processing Clocks throughput

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A High-Speed FPGA Implementation of the Multidimensional Reconciliation for Continuous Variables Quantum Key Distribution

A High-Speed FPGA Implementation of the Multidimensional Rec...

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Communication, Image and Signal processing (CCISP), international conference on

作者： Jialu Sun Hao Cheng Zeyuan Jin Yong Chen Genlong Chen Lihong Ren Xueqin Jiang School of Information Science and Technology Donghua University Shanghai China

ISBN: (数字)9798350356656

ISBN: (纸本)9798350356663

For continuous variable quantum key distribution (CV-QKD) protocol, information reconciliation (IR) is a key step that can significantly affect the performance of CV-QKD. Because of multidimensional reconciliation suitable for low signal-to-noise ratio (SNR) and long transmission distance scenario, a parallel architecture for the multidimensional reconciliation in CV-QKD implemented on field programmable gate array (FPGA) is proposed in this paper. Using a binarized d-dimensional spherical vector c and a parallel computation of the coefficient a and rotation matrix M, the parallel architecture achieves 45.635 Mbps processing throughput at 250 MHz in the system clock, with frame error rate (FER) less than 0.001 when the SNR exceeds 0.71 dB.

关键词： Protocols Signal processing algorithms throughput Vectors Real-time systems Quantum key distribution parallel architectures Field programmable gate arrays Signal to noise ratio Pipeline processing

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Hardware Implementation Analysis of the MD5 Hash Algorithm

Hardware Implementation Analysis of the MD5 Hash Algorithm

引用

Annual Hawaii international conference on System Sciences (HICSS)

作者： K. Jarvinen M. Tommiska J. Skytta Signal Processing Laboratory Helsinki University of Technology Finland

Hardware implementation aspects of the MD5 hash algorithm are discussed in this paper. A general architecture for MD5 is proposed and several implementations are presented. An extensive study of effects of pipelining on delay, area requirements and throughput is performed, and finally certain architectures are recommended and compared to other published MD5 designs. the designs were implemented on a Xilinx Virtex-II XC2V4000-6 FPGA and a throughput of 586 Mbps was achieved with logic requirements of only 647 slices and 2 BlockRAMs. Methods to increase the throughput to gigabit-level were also studied and an implementation of parallel MD5 blocks achieving a throughput of over 5.8 Gbps was introduced. At least to the authors' knowledge, MD5 designs presented in this paper are the fastest published FPGA-based architectures at the time of writing.

关键词： Hardware Algorithm design and analysis Signal processing algorithms throughput Field programmable gate arrays Acceleration Table lookup Logic design Logic devices Signal design

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A Mapping Method for Application Customized Reconfigurable Pipeline

A Mapping Method for Application Customized Reconfigurable P...

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international conference on Networking, Architecture, and Storage (NAS)

作者： Guanwu Wang Sikun Li School of Computer National University of Defense Technology Changsha China

Application mapping algorithm for reconfigurable architecture is one of the major research direction in reconfigurable computing. In this paper, we analyze the data memory bank conflict problem of the ACRPs (Application Customized Reconfigurable Pipelines) when exploiting the data parallelism and a conflict-free iteration-data mapping algorithm based on the operation mapping results is proposed to conquer the bank conflict problem. the experiments showed that ACRP can exploit the CFU, pipeline- and data-level parallelism efficiently. More specifically, the iteration-data mapping algorithm avoids the bank conflicts while exploiting the data parallelism to increase the throughput.

关键词： Arrays Kernel Reconfigurable architectures parallel processing Pipelines Clustering algorithms

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Impact of Loop Tiling on the Controller Logic of Acceleration Engines

Impact of Loop Tiling on the Controller Logic of Acceleratio...

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IEEE international conference on Application-specific Systems, architectures and Processors

作者： Hritam Dutta Jiali Zhai Frank Hannig Jurgen Teich Hardware/Software Co-Design Department of Computer Science University of Erlangen-Nuremberg Hardware/Software Co-Design Department of ComputerScience University of Erlangen-Nuremberg

ISBN: (纸本)9781424445523

High computational effort in modern signal and image processing applications often demands for special purpose accelerators in a system on chip (SoC). New high level synthesis methodologies enable the automated design of such programmable or non-programmable accelerators. Loop tiling is a widely used transformation in such methodologies for dimensioning of such accelerators in order to match inherent massive parallelism of considered algorithms with available functional units and processor elements. Innately, the applications are data-flow dominant and have almost no control flow, but the application of tiling techniques has the disadvantage of a more complex control and communication flow. In this paper, we present a methodology for the automatic generation of the control engines of such accelerators. the controller orchestrates the data transfer and computation. the effect of tiling on area, latency, and power overhead of the controller is studied in detail. It is shown that the controller has a substantial overhead of up to 50% in for different tiling and throughput parameters. the energy-delay product is also used as a metric for identifying optimal accelerator designs.

关键词： Logic Acceleration Engines Automatic control Communication system control Signal processing Image processing System-on-a-chip High level synthesis parallel processing

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