this paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniqu...
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this paper presents a path of parallelism exploitation in commercial programmable DSP processors. DSP processors have gained in their complexity and have adopted some very sophisticated parallelism extraction techniques, namely very long instruction word (VLIW) and SIMD designs. the intention is to show a development path of digital signal processors (DSP) and focuses on their features that allow parallelprocessing of algorithms.
the paper explores a number of possible hardware architectures for implementing synchronous dataflow (SDF) models of digital signal processing (DSP) applications in reconfigurable logic components, for example, Field ...
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In this paper, a pipelined architecture for inverse discrete cosine transform (IDCT) is presented. Pipeline architectures are popular in parallel fast Fourier transform implementations but they are rare in IDCT implem...
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In this paper, a pipelined architecture for inverse discrete cosine transform (IDCT) is presented. Pipeline architectures are popular in parallel fast Fourier transform implementations but they are rare in IDCT implementations due to the irregularities in fast IDCT algorithms. the proposed architecture is derived by applying vertical projection to in-place IDCT algorithm. the resulting structure is modular and easy to pipeline. the word width requirements in the internal arithmetic are estimated to fulfil the requirements set by IEEE standard for 8×8 inverse cosine transform.
Exploitation of data re-use in combination withthe use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, especially for data-intensive applicatio...
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ISBN:
(纸本)3540410686
Exploitation of data re-use in combination withthe use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, especially for data-intensive applications. the effect of the data-reuse decisions on the power dissipation but also on area and performance of multimedia applications realized on multiple embedded cores is explored. the interaction between the data-reuse decisions and the selection of a certain data-memory architecture model is also studied, As demonstrator a widely-used video processing algorithmic kernel, namely the full search motion estimation kernel, is used. Experimental results prove that improvements in both power and performance can be acquired, when the right combination of data memory architecture model and data-reuse transformation is selected.
Solving Boolean satisfiability problems in reconfigurable hardware is an area of great research interest. Originally, reconfigurable hardware was used to map each problem instance and thus exploit maximum parallelism ...
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this paper adopts a transformational programming approach for deriving massively parallelalgorithms from functional specifications. It gives a brief description of a framework for relating key higher order functions ...
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ISBN:
(纸本)0780365429
this paper adopts a transformational programming approach for deriving massively parallelalgorithms from functional specifications. It gives a brief description of a framework for relating key higher order functions such as map, reduce, and scan with communicating processes with different configurations. the parallelisation of many interesting functional algorithms can then be systematically synthesized by combining "off the shelf" parallel implementations of instances of these higher order functions. Efficiency in the final message-passing algorithms is achieved by exploiting data parallelism, for generating the intermediate results in parallel; and functional parallelism, for processing intermediate results in stages such that the output of one stage is simultaneously input to the next one. this approach is illustrated through a case study for testing whether all the elements of a given list are distinct. Bird-Meertens formalism is used to concisely carry out algebraic transformations.
the evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. the system designers are faced with ...
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the evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. the system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. this paper presents first the major challenges in realizing flexible microelectronic system solutions for digital baseband signal processing in future mobile communication applications. Based thereupon, the architecture design of flexible system-on-a-chip solutions is discussed. the focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.
Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tre...
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ISBN:
(纸本)9643600572
Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tree multiplier, combined modified Booth-Wallace tree multiplier and twin pipe serial parallel multiplier. Comparison is based on synthesis results obtained by synthesizing all multiplier architectures towards FPGA.
作者：
Kim, KUniv Seoul
Sch Elect Engn Dongdaemun Gu Seoul 130743 South Korea
this paper proposes a new memory system called shuffle memory. the shuffle memory is a generalization of transposition mentor that has been widely used in 2-D Discrete Cosine Transform and Discrete Fourier Transform. ...
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ISBN:
(纸本)0769501435
this paper proposes a new memory system called shuffle memory. the shuffle memory is a generalization of transposition mentor that has been widely used in 2-D Discrete Cosine Transform and Discrete Fourier Transform. the shuffle memory is the first memory system that receives M x N inputs in row major while providing M x N outputs in column major order using only M x N memory space. Shuffle memory can provide memory efficient architectures for separable 2-D transforms and separable 2-D filter banks.
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